公开(公告)号：US07848129B1

公开(公告)日：2010-12-07

申请号：US12275160

申请日：2008-11-20

Applicant: Chetan Deshpande ,  Vinay Iyengar ,  Bindiganavale S. Nataraj

Inventor： Chetan Deshpande ,  Vinay Iyengar ,  Bindiganavale S. Nataraj

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array includes a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein the control circuit has an input to receive a corresponding sub-array enable signal. The partition logic has an input to receive a partition select signal, and is configured to generate the sub-array enable signals in response to the partition select signal. The control circuits selectively propagate the search key through the sub-arrays in response to the sub-array enable signals.

Abstract translation: 内容可寻址存储器（CAM）装置包括比较寄存器，CAM阵列和分区逻辑。 比较寄存器具有用于接收搜索关键字的输入，并且耦合到CAM阵列的输出，其包括多个可单独选择的子阵列。 每个子阵列包括多个CAM单元行和一个控制电路，其中每行CAM单元耦合到匹配线，并且其中控制电路具有用于接收对应的子阵列使能信号的输入。 分区逻辑具有用于接收分区选择信号的输入，并且被配置为响应于分区选择信号而生成子阵列使能信号。 响应于子阵列使能信号，控制电路通过子阵列选择性地传播搜索关键字。

公开(公告)号：US07840783B1

公开(公告)日：2010-11-23

申请号：US11852916

申请日：2007-09-10

Applicant: Gaurav Singh ,  Srivatsan Srinivasan ,  Ricardo Ramirez ,  Wei-Hsiang Chen ,  Hai Ngoc Nguyen

Inventor： Gaurav Singh ,  Srivatsan Srinivasan ,  Ricardo Ramirez ,  Wei-Hsiang Chen ,  Hai Ngoc Nguyen

IPC: G06F9/00 ,  G06F9/44

CPC classification number: G06F9/384 ,  G06F9/30112 ,  G06F9/30189

Abstract: A system, method, and computer program product are provided for performing a register renaming operation utilizing hardware which operates in at least two modes. In operation, hardware is operated in at least two modes including a first mode for operating the hardware using a logical register of a first bit width and a second mode for operating the hardware using a logical register of a second bit width. The first bit width is twice a width of the second bit width. Additionally, a register renaming operation is performed, including renaming at least one logical register to at least one physical register of the first bit width, utilizing the hardware.

Abstract translation: 提供了一种系统，方法和计算机程序产品，用于使用以至少两种模式操作的硬件来执行注册重命名操作。 在操作中，硬件以至少两种模式运行，包括使用第一位宽度的逻辑寄存器操作硬件的第一模式和使用第二位宽的逻辑寄存器来操作硬件的第二模式。 第一位宽度是第二位宽度的两倍。 此外，执行寄存器重命名操作，包括利用硬件将至少一个逻辑寄存器重命名为至少一个第一位宽的物理寄存器。

公开(公告)号：US07836246B2

公开(公告)日：2010-11-16

申请号：US12214952

申请日：2008-06-23

Applicant: Mark Birman ,  Ajay Srikrishna ,  Srinivasan Venkatachary

Inventor： Mark Birman ,  Ajay Srikrishna ,  Srinivasan Venkatachary

IPC: G06F13/00

CPC classification number: G11C15/00 ,  Y10S707/99936

Abstract: A content addressable memory device (100) and method can have CAM blocks (102-0 to 102-29) organized in block sections (104-0 to 104-6). In an overlay mode of operation, an overlay engine (106) can access an algorithmic search (SPEAR) CAM (102-28 and 102-29) to generate overlay data set search keys (keyFIB and ). Multiple data sets (e.g., FIB0, FIB1, ACL0) can be accommodated on the same CAM device by search key multiplexers (108-0 to 108-6) that selectively apply any of a number of data set search keys (keyACL , keyFIB and keyFIB ).

Abstract translation: 内容可寻址存储器件（100）和方法可以具有以块部分（104-0至104-6）组织的CAM块（102-0至102-29）。 在覆盖操作模式中，覆盖引擎（106）可以访问算法搜索（SPEAR）CAM（102-28和102-29）以生成覆盖数据集搜索关键字（keyFIB <0>和<1>）。 多个数据集（例如，FIB0，FIB1，ACL0）可以通过搜索关键多路复用器（108-0至108-6）容纳在相同的CAM设备上，该多路复用器选择性地应用多个数据集搜索键（keyACL < ，keyFIB <0>和keyFIB <1>）。

公开(公告)号：US07830691B2

公开(公告)日：2010-11-09

申请号：US12175272

申请日：2008-07-17

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna ,  Bindiganavale S. Nataraj

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna ,  Bindiganavale S. Nataraj

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.

Abstract translation: 低功率内容可寻址存储器（CAM）设备。 CAM设备接收N位比较值，并且作为响应，在CAM设备内激活小于N个比较线，以将比较值的N个比特中的每一个与耦合到N个比较线的CAM小区的内容进行比较。

公开(公告)号：US07822916B1

公开(公告)日：2010-10-26

申请号：US11554958

申请日：2006-10-31

Applicant: Tingjun Wen

Inventor： Tingjun Wen

IPC: G06F12/00

CPC classification number: G11C15/00

Abstract: A search engine device includes a lookup circuit, such as a content addressable memory (CAM) array. This lookup circuit is configured to generate multiple active match signals in response to detecting multiple matches between a search operand applied to said lookup circuit and multiple entries therein, during a search operation. A priority sequencer circuit is also provided. This priority sequencer circuit, which is electrically coupled to outputs of the lookup circuit, is configured to sequentially encode each of the multiple active match signals according to priority.

Abstract translation: 搜索引擎设备包括诸如内容可寻址存储器（CAM）阵列之类的查找电路。 该查找电路被配置为响应于在搜索操作期间检测应用于所述查找电路的搜索操作数和其中的多个条目之间的多个匹配来生成多个有效匹配信号。 还提供优先顺序器电路。 电耦合到查找电路的输出的该优先顺控器电路被配置为根据优先顺序对多个有效匹配信号中的每一个进行顺序编码。

公开(公告)号：US07814267B1

公开(公告)日：2010-10-12

申请号：US12012618

申请日：2008-02-04

Applicant: Vinay Raja Iyengar ,  Venkat Rajendher Reddy Gaddam ,  Aparna Bharat

Inventor： Vinay Raja Iyengar ,  Venkat Rajendher Reddy Gaddam ,  Aparna Bharat

IPC: G06F13/00 ,  G06F13/28

CPC classification number: G06F17/30982

Abstract: A processor device integrated circuit can include a plurality of storage locations logically configurable into at least one database. Such a database can include a number of records, record having a selectable size of up to F multi-bit segments, where F is an integer greater than one. A search key application circuit can apply a search key value of up to F multi-bit segments to the at least one database in response to receiving one search key segment value. The one search key segment can be applied as any of the F multi-bit segments according to a segment selection value.

Abstract translation: 处理器设备集成电路可以包括逻辑上可配置到至少一个数据库中的多个存储位置。 这样的数据库可以包括多个记录，具有至多F多位段的可选择大小的记录，其中F是大于1的整数。 响应于接收到一个搜索关键字段值，搜索关键字应用电路可以向至少一个数据库应用多达F个多位分段的搜索关键字值。 可以根据段选择值将一个搜索关键段应用为F多位段中的任何一个。

公开(公告)号：US07801877B1

公开(公告)日：2010-09-21

申请号：US12102282

申请日：2008-04-14

Applicant: Gary Depelteau ,  Pascal de Wit

Inventor： Gary Depelteau ,  Pascal de Wit

IPC: G06F7/00

CPC classification number: G06F17/30982

Abstract: Integrated circuit search engine devices include serially connected stages, a handle memory and a handle memory access manager. The stages store search keys in a multilevel tree of search keys. A first level stage is responsive to an input search key and a last level stage identifies a best match key for the input search key. The handle memory includes handle memory locations that store search result handles. The handle memory access manager searches the handle memory to retrieve a search result handle that corresponds to a best match key. The handle memory access manager refrains from modifying the handle memory in response to modify instructions during active periods of the handle memory when the handle memory is being searched. The handle memory access manager modifies the handle memory in response to the modify instructions during idle periods of the handle memory when the handle memory is not being searched. Related methods are also disclosed.

Abstract translation: 集成电路搜索引擎设备包括串行连接的级，句柄存储器和句柄存储器访问管理器。 阶段将搜索键存储在多级搜索键树中。 第一级响应于输入搜索关键字，最后一级标识输入搜索关键字的最佳匹配键。 句柄存储器包括存储搜索结果句柄的句柄存储器位置。 句柄存储器访问管理器搜索句柄存储器以检索对应于最佳匹配键的搜索结果句柄。 当正在搜索句柄存储器时，句柄存储器访问管理器避免修改句柄存储器以响应于句柄存储器的活动期间的修改指令。 当句柄存储器未被搜索时，句柄存储器访问管理器响应于句柄存储器的空闲周期期间的修改指令来修改句柄存储器。 还公开了相关方法。

公开(公告)号：US07782645B1

公开(公告)日：2010-08-24

申请号：US12012660

申请日：2008-02-04

Applicant: Venkat Rajendher Reddy Gaddam ,  Rajagopal Krishnaswamy ,  Vinay Raja Iyengar

Inventor： Venkat Rajendher Reddy Gaddam ,  Rajagopal Krishnaswamy ,  Vinay Raja Iyengar

IPC: G11C15/00

CPC classification number: G11C15/00 ,  G11C7/1006

Abstract: An integrated circuit device can include a plurality of configuration storage locations each comprising at least one encoding field. Each encoding field can selectively enable at least one received data value to be encoded into an encoded data value prior to being applied to a corresponding block of the integrated circuit device. Each block can comprise a plurality of content addressable memory (CAM) cells.

Abstract translation: 集成电路设备可以包括多个配置存储位置，每个配置存储位置包括至少一个编码字段。 每个编码字段可以选择性地使得至少一个接收的数据值被编码为编码数据值，然后再应用于集成电路器件的对应块。 每个块可以包括多个内容可寻址存储器（CAM）单元。

公开(公告)号：US07697518B1

公开(公告)日：2010-04-13

申请号：US11532225

申请日：2006-09-15

Applicant: Pascal de Wit

Inventor： Pascal de Wit

IPC: H04L12/28 ,  H04L12/56

CPC classification number: G06F17/30961 ,  G06F17/30985

Abstract: Methods of updating b-tree data structures (e.g., b*tree data structure) using search key insertion and deletion operations proceed from respective known states (e.g., respective canonical forms). These insertion operations include inserting a first search key into the b-tree by reconfiguring (e.g., pre-processing) a plurality of sibling nodes of the b-tree into a predetermined overloaded form having a shape that is independent of a value of the first search key to be inserted therein. An operation is then performed to split the sibling nodes by redistributing the first and other search keys among an expanded plurality of the sibling nodes. These insertion operations use a process that trades off possibly performing additional memory accesses (e.g., to shift search keys (and/or handles or pointers) to the predetermined overloaded form) for the certainty that the same key movements are ultimately performed during operations to split sibling nodes.

Abstract translation: 使用搜索关键字插入和删除操作来更新b-tree数据结构（例如，b *树数据结构）的方法从相应的已知状态（例如，相应的规范形式）进行。 这些插入操作包括通过将b-树的多个兄弟节点重新配置（例如，预处理）成预定的重载形式，将第一搜索密钥插入到b树中，该预定重载形式具有独立于第一 搜索键插入其中。 然后执行操作以通过在扩展的多个兄弟节点中重新分配第一和其他搜索关键来拆分兄弟节点。 这些插入操作使用可能执行附加存储器访问的过程（例如，将搜索键（和/或句柄或指针）移位到预定的重载形式），以确定在分割操作期间最终执行相同的键移动 兄弟节点。

公开(公告)号：US07643353B1

公开(公告)日：2010-01-05

申请号：US12131992

申请日：2008-06-03

Applicant: Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

Inventor： Maheshwaran Srinivasan ,  Varadarajan Srinivasan ,  Sandeep Khanna ,  Sachin Joshi ,  Mark Birman

IPC: G11C7/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match line that indicates a match result for the CAM row. The programmable interconnect structure is coupled to each CAM row and is configured to selectively route the match results from a first CAM row as an input match signal to any number of arbitrarily selected CAM rows at the same time.

Abstract translation: 内容可寻址存储器（CAM）装置包括CAM阵列，可编程互连结构和优先编码器。 CAM阵列包括多个CAM行，每行包括用于存储数据字并耦合到指示CAM行的匹配结果的匹配线的多个CAM单元。 可编程互连结构耦合到每个CAM行，并且被配置为选择性地将来自第一CAM行的匹配结果作为输入匹配信号同时路由到任意数量的任意选择的CAM行。