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公开(公告)号：US20080270774A1
公开(公告)日：2008-10-30
申请号：US11799293
申请日：2007-04-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.
摘要翻译： 投机分支预测系统。 该系统的实施例包括分支预测逻辑，提取逻辑和分支识别逻辑。 分支预测逻辑被配置为预测指令流中的分支的分支路径。 提取逻辑耦合到分支预测逻辑。 提取逻辑被配置为推测性地获取与预测的分支路径相对应的指令。 分支识别逻辑耦合到分支预测逻辑和提取逻辑。 分支识别逻辑被配置为使用通用分支标识格式使用分支标识符标记所推测的获取的指令。 通用分支识别格式包括与预测分支路径相对应的比特位置处的比特值。
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2.发明授权System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths 有权利用能够利用多个宽度的寄存器的至少两种模式进行操作的硬件来执行使用硬件的寄存器重命名操作的系统和方法公开(公告)号：US07840783B1
公开(公告)日：2010-11-23
申请号：US11852916
申请日：2007-09-10
CPC分类号： G06F9/384 , G06F9/30112 , G06F9/30189
摘要： A system, method, and computer program product are provided for performing a register renaming operation utilizing hardware which operates in at least two modes. In operation, hardware is operated in at least two modes including a first mode for operating the hardware using a logical register of a first bit width and a second mode for operating the hardware using a logical register of a second bit width. The first bit width is twice a width of the second bit width. Additionally, a register renaming operation is performed, including renaming at least one logical register to at least one physical register of the first bit width, utilizing the hardware.
摘要翻译： 提供了一种系统，方法和计算机程序产品，用于使用以至少两种模式操作的硬件来执行注册重命名操作。 在操作中，硬件以至少两种模式运行，包括使用第一位宽度的逻辑寄存器操作硬件的第一模式和使用第二位宽的逻辑寄存器来操作硬件的第二模式。 第一位宽度是第二位宽度的两倍。 此外，执行寄存器重命名操作，包括利用硬件将至少一个逻辑寄存器重命名为至少一个第一位宽的物理寄存器。
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公开(公告)号：US07711935B2
公开(公告)日：2010-05-04
申请号：US11799293
申请日：2007-04-30
IPC分类号： G06F9/32
CPC分类号： G06F9/3842 , G06F9/3861
摘要： A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path.
摘要翻译： 投机分支预测系统。 该系统的实施例包括分支预测逻辑，提取逻辑和分支识别逻辑。 分支预测逻辑被配置为预测指令流中的分支的分支路径。 提取逻辑耦合到分支预测逻辑。 提取逻辑被配置为推测性地获取与预测的分支路径相对应的指令。 分支识别逻辑耦合到分支预测逻辑和提取逻辑。 分支识别逻辑被配置为使用通用分支标识格式使用分支标识符标记所推测的获取的指令。 通用分支识别格式包括与预测分支路径相对应的比特位置处的比特值。
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4.发明申请SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CREATING DEPENDENCIES AMONGST INSTRUCTIONS USING TAGS 审中-公开系统，方法和计算机程序产品在使用标签的指令中创建相关性公开(公告)号：US20090259827A1
公开(公告)日：2009-10-15
申请号：US12102473
申请日：2008-04-14
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857
摘要： A system, method, and computer program product are provided for creating dependencies amongst instructions using tags. In operation, tags are associated with a first instruction and a second instruction. Additionally, a dependency is created between the first instruction and the second instruction, utilizing the tags. Furthermore, the first instruction and the second instruction are executed in accordance with the dependency.
摘要翻译： 提供了一种系统，方法和计算机程序产品，用于在使用标签的指令之间创建依赖关系。 在操作中，标签与第一指令和第二指令相关联。 此外，利用标签在第一指令和第二指令之间产生依赖性。 此外，根据依赖性来执行第一指令和第二指令。
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公开(公告)号：US20080320478A1
公开(公告)日：2008-12-25
申请号：US11830727
申请日：2007-07-30
IPC分类号： G06F9/46
CPC分类号： G06F9/3814 , G06F9/3838
摘要： An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector.
摘要翻译： 一种用于队列分配的装置。 该装置的实施例包括调度顺序数据结构，位向量和队列控制器。 调度订单数据结构对应于一个队列。 调度订单数据结构存储与队列的多对条目相关联的多个调度指示符，以指示队列中条目的写入顺序。 位向量存储对应于调度顺序数据结构的调度指示符的多个掩码值。 队列控制器与队列和调度订单数据结构接口。 队列控制器基于位向量的掩码值从队列操作中排除至少一些条目。
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公开(公告)号：US20080320016A1
公开(公告)日：2008-12-25
申请号：US11847170
申请日：2007-08-29
CPC分类号： G06F9/3836 , G06F9/3855 , H04L47/50 , H04L49/90 , H04L49/901
摘要： An apparatus for queue scheduling. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The queue controller interfaces with the queue and the dispatch order data structure. Multiple queue structures interfaces with an output arbitration logic and schedule packets to achieve optimal throughput.
摘要翻译： 一种用于队列调度的装置。 该装置的实施例包括调度顺序数据结构，位向量和队列控制器。 调度订单数据结构对应于一个队列。 调度订单数据结构存储与队列的多对条目相关联的多个调度指示符，以指示队列中条目的写入顺序。 队列控制器与队列和调度订单数据结构接口。 多队列结构与输出仲裁逻辑接口并调度数据包以实现最佳吞吐量。
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公开(公告)号：US20080320274A1
公开(公告)日：2008-12-25
申请号：US11820350
申请日：2007-06-19
IPC分类号： G06F9/30
CPC分类号： G06F9/3814 , G06F9/3838
摘要： An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector.
摘要翻译： 一种用于队列分配的装置。 该装置的实施例包括调度顺序数据结构，位向量和队列控制器。 调度订单数据结构对应于一个队列。 调度订单数据结构存储与队列的多对条目相关联的多个调度指示符，以指示队列中条目的写入顺序。 位向量存储对应于调度顺序数据结构的调度指示符的多个掩码值。 队列控制器与队列和调度订单数据结构接口。 队列控制器基于位向量的掩码值从队列操作中排除至少一些条目。
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公开(公告)号：US08285974B2
公开(公告)日：2012-10-09
申请号：US11830727
申请日：2007-07-30
IPC分类号： G06F9/30
CPC分类号： G06F9/3814 , G06F9/3838
摘要： An apparatus for queue allocation. An embodiment of the apparatus includes a dispatch order data structure, a bit vector, and a queue controller. The dispatch order data structure corresponds to a queue. The dispatch order data structure stores a plurality of dispatch indicators associated with a plurality of pairs of entries of the queue to indicate a write order of the entries in the queue. The bit vector stores a plurality of mask values corresponding to the dispatch indicators of the dispatch order data structure. The queue controller interfaces with the queue and the dispatch order data structure. The queue controller excludes at least some of the entries from a queue operation based on the mask values of the bit vector.
摘要翻译： 一种用于队列分配的装置。 该装置的实施例包括调度顺序数据结构，位向量和队列控制器。 调度订单数据结构对应于一个队列。 调度订单数据结构存储与队列的多对条目相关联的多个调度指示符，以指示队列中条目的写入顺序。 位向量存储对应于调度顺序数据结构的调度指示符的多个掩码值。 队列控制器与队列和调度订单数据结构接口。 队列控制器基于位向量的掩码值从队列操作中排除至少一些条目。
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公开(公告)号：US20110013643A1
公开(公告)日：2011-01-20
申请号：US12890551
申请日：2010-09-24
IPC分类号： H04L12/56
CPC分类号： H04L49/25 , H04L49/101 , H04L49/3027 , H04L49/3045
摘要： The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. Whereby, the arbiter circuit scans the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs. The invention also relates to a crossbar switch controller including an arbitration pre-processor coupled to the input terminal and the matrix circuit, and configured to represent the set of service request signals in the form of a mapping matrix, and further configured to transform a first mapping position of the service request signal to a second mapping position based, in part, on a mapping algorithm. The invention also includes an arbitration post-processor coupled to the output terminal and the matrix circuit, and further configured to transform the second mapping position of the service request signal back to the first mapping position.
摘要翻译： 本发明涉及一种交叉开关控制器，其包括输入端子，该输入端子被配置为从包括一组分组的一组虚拟输出队列接收一组服务请求信号。 本发明还包括耦合到输入端并被配置为以矩阵的形式表示服务请求信号集合的矩阵电路，其中每个服务请求信号由行位置M和列位置N描述。本发明进一步 包括被配置为在历元期间接收所述一组分组的一部分的输出终端，所述仲裁器电路被配置为在所述时期期间迭代地扫描所述矩阵，并向所述虚拟输出队列发出所述一组授权信号以确定哪些服务请求被授权， 以及仲裁器控制器，被配置为使用非冲突矩阵元素的阵列启动仲裁器电路。 由此，仲裁器电路在第一纪元期间扫描矩阵，发出授权信号集合，允许一组授权的服务请求基本上完成，并且如果需要，在随后的时期期间扫描矩阵。 本发明还涉及一种交叉开关控制器，其包括耦合到输入端和矩阵电路的仲裁预处理器，并且被配置为以映射矩阵的形式表示该组服务请求信号，并且还被配置为将第一 部分地基于映射算法将服务请求信号的映射位置映射到第二映射位置。 本发明还包括耦合到输出端和矩阵电路的仲裁后处理器，还被配置为将服务请求信号的第二映射位置转换回第一映射位置。
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公开(公告)号：US20050122972A1
公开(公告)日：2005-06-09
申请号：US10968460
申请日：2004-10-18
申请人： Frederick Gruner , Gaurav Singh , Elango Ganesan , Samir Vora , Christopher Eccles , Brian Wai Yang
发明人： Frederick Gruner , Gaurav Singh , Elango Ganesan , Samir Vora , Christopher Eccles , Brian Wai Yang
CPC分类号： H04L29/12801 , H04L29/12009 , H04L45/00 , H04L45/7457 , H04L61/6004
摘要： A prefix matching apparatus for directing information to a destination port includes a memory configured to store a piece of data including an address and a plurality of levels each including a plurality of memory locations, the levels each representing a unique address space. A controller is coupled to the memory and to the plurality of levels, and is configured to read the data address and to direct the data to the next level associated with a unique address space associated with the data address. In one embodiment, the controller is configured to match the data address prefix to a plurality of addresses associated with the unique address spaces. Advantages of the invention include fast switch decisions and low switch latency.
摘要翻译： 用于将信息引导到目的地端口的前缀匹配装置包括被配置为存储包括地址和多个级别的数据的存储器，每个级别包括多个存储器位置，每个级别表示唯一的地址空间。 控制器耦合到存储器和多个电平，并且被配置为读取数据地址并将数据引导到与与数据地址相关联的唯一地址空间相关联的下一级。 在一个实施例中，控制器被配置为将数据地址前缀匹配到与唯一地址空间相关联的多个地址。 本发明的优点包括快速切换决定和低开关等待时间。
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