公开(公告)号：US11348870B2

公开(公告)日：2022-05-31

申请号：US16918053

申请日：2020-07-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US20220165663A1

公开(公告)日：2022-05-26

申请号：US17104078

申请日：2020-11-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Vibhor Jain ,  Yves T. Ngu ,  Johnatan A. Kantarovsky ,  Alain F. Loiseau

IPC: H01L23/525 ,  H01L27/07 ,  H01L21/02 ,  H01L21/8249

Abstract: An electrical fuse (e-fuse) includes a fuse link including a silicided semiconductor layer over a dielectric layer covering a gate conductor. The silicided semiconductor layer is non-planar and extends orthogonally over the gate conductor. A first terminal is electrically coupled to a first end of the fuse link, and a second terminal is electrically coupled to a second end of the fuse link. The fuse link may be formed in the same layer as an intrinsic and/or extrinsic base of a bipolar transistor. The gate conductor may control a current source for programming the e-fuse. The e-fuse reduces the footprint and the required programming energy compared to conventional e-fuses.

公开(公告)号：US11340403B2

公开(公告)日：2022-05-24

申请号：US16807942

申请日：2020-03-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/35 ,  G02B6/293 ,  G02B6/36 ,  G02B6/42 ,  G02B6/12 ,  G02B6/122

Abstract: One illustrative device disclosed herein includes a layer of semiconductor material and a first Bragg reflector structure positioned in the layer of semiconductor material, wherein the first Bragg reflector structure comprises a plurality of dielectric elements and a first internal area defined by an innermost of the first plurality of dielectric elements. In this example, the device also includes an optical component positioned above the layer of semiconductor material, wherein at least a portion of the optical component is positioned within a vertical projection of the first internal area.

公开(公告)号：US20220155535A1

公开(公告)日：2022-05-19

申请号：US17099834

申请日：2020-11-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Siva P. Adusumilli ,  Mark D. Levy

IPC: G02B6/42 ,  H01L31/0256 ,  H01L31/02

Abstract: A photodetector array includes a substrate, and an array of pixels over the substrate. Each pixel includes a set of diffraction gratings directly on a semiconductor photodetector. A pitch of the set of diffraction gratings associated with each pixel in the array of pixels are different to enable each pixel to detect a specific wavelength of light different than other pixels of the array of pixels. An air cavity may be provided in the substrate under the germanium photodetector to improve light absorption. A method of forming the photodetector array is also disclosed.

公开(公告)号：US20220148633A1

公开(公告)日：2022-05-12

申请号：US17092384

申请日：2020-11-09

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Xiaoxiao Li ,  Lei Zhang

IPC: G11C7/22 ,  G11C7/10

Abstract: Embodiments of the disclosure provide systems and methods for transmitting clock signals asynchronously to dual-port memory cells. A system according to embodiments of the disclosure may include a source clock configured to generate a clock signal, a dual-port memory cell having a first input port, and a second input port coupled to the source clock. A clock tuner coupled between the source clock and the first input port of the dual-port memory cell delays the clock signal by one of a plurality of delay times and transmits the clock signal to the first input port.

公开(公告)号：US20220140131A1

公开(公告)日：2022-05-05

申请号：US17087681

申请日：2020-11-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Avinash Lahgere ,  Prashanth Paramahans Manik ,  Peter Javorka ,  Ali Icel ,  Mohit Bajaj

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786

Abstract: A transistor includes a semiconductor substrate, a first source/drain region and a second source/drain region in the semiconductor substrate with a channel region between the source/drain regions, and a gate over the channel region. In addition, the transistor includes a first phase transition material (PTM) region between the first source/drain region and the channel region, and a second PTM region between the second source/drain region and the channel region. The PTM regions provide the transistor with improved off-state current (IOFF) without affecting the on-state current (ION), and thus an improved ION/IOFF ratio. The transition threshold of PTM regions from dielectric to conductor can be customized based on, for example, PTM material type, doping therein, and/or strain therein.

公开(公告)号：US20220137290A1

公开(公告)日：2022-05-05

申请号：US17087182

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Abdelsalam A. ABOKETAF ,  Won Suk LEE ,  Yusheng BIAN

IPC: G02B6/028 ,  G02B6/122

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multi-mode optical waveguide structures with isolated absorbers and methods of manufacture. The structure includes: a waveguide structure including tapered segments; and at least one isolated waveguide absorber adjacent to the waveguide structure along its length.

公开(公告)号：US11320590B2

公开(公告)日：2022-05-03

申请号：US16836047

申请日：2020-03-31

Applicant: GLOBALFOUNDRIES U.S. Inc. ,  KHALIFA UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Yusheng Bian ,  Sujith Chandran ,  Jaime Viegas ,  Humarira Zafar ,  Ajey Poovannummoottil Jacob

IPC: G02B6/26 ,  G02B6/125 ,  G02B6/126 ,  G02B6/13 ,  G02B6/12

Abstract: Structures for a polarizer and methods of fabricating a structure for a polarizer. A waveguide crossing includes a first arm and a second arm. A waveguide loop couples the first arm of the waveguide crossing to the second arm of the waveguide crossing. The waveguide crossing and the waveguide loop provide a structure for the polarizer.

公开(公告)号：US11320589B1

公开(公告)日：2022-05-03

申请号：US17084186

申请日：2020-10-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Siva P. Adusumilli ,  Bo Peng ,  Kenneth J. Giewont

IPC: G02B6/124 ,  G02B6/12 ,  G02B6/13

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers integrated with one or more airgap and methods of manufacture. The structure includes: a substrate material comprising one or more airgaps; and a grating coupler disposed over the substrate material and the one or more airgaps.

公开(公告)号：US11315835B2

公开(公告)日：2022-04-26

申请号：US16296469

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Wei Hong ,  Hong Yu ,  Tao Chu ,  Bingwu Liu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/308

Abstract: One illustrative method disclosed herein includes forming a conformal SMCM layer above a conformal high-k gate insulation layer within each of first and second replacement gate cavities (RGC), removing the SMCM layer from the first RGC while leaving the SMCM layer in position within the second RGC, forming a first conformal metal-containing material (MCM) layer above the gate insulation layer within the first RGC and above the SMCM layer in position within the second RGC, removing the first conformal MCM layer and the conformal SMCM layer positioned within the second RGC while leaving the first conformal MCM layer within the first RGC, and forming a second conformal MCM layer above the first conformal MCM layer positioned within the first RGC and above the gate insulation layer positioned within the second RGC.