公开(公告)号：US07565482B1

公开(公告)日：2009-07-21

申请号：US11638649

申请日：2006-12-13

Applicant: Anand Rangarajan ,  Srinivasan Venkatachary

Inventor： Anand Rangarajan ,  Srinivasan Venkatachary

IPC: G06F12/00

CPC classification number: G11C15/00 ,  G06F17/30982

Abstract: A search engine system (100) compares search key values to stored entry values, and includes first blocks of entries (102) and second blocks of entries (104). First blocks of entries (102) can be “search” blocks that can provide a relatively fast search speed of stored data value, and each store a unique first portion of one or more entry values. Second blocks of entries (104) can be randomly accessible entries logically arranged into search nodes that each correspond to a first portion of an entry value stored in the first block of entries. Each search node can include one or more second portions of an entry value.

Abstract translation: 搜索引擎系统（100）将搜索关键字值与存储的条目值进行比较，并且包括条目（102）的第一块和条目（104）的第二块。 条目（102）的第一块可以是可以提供存储的数据值的相对较快的搜索速度的“搜索”块，并且每个块存储一个或多个条目值的唯一的第一部分。 条目（104）的第二块可以是逻辑上排列到搜索节点中的随机访问条目，每个对应于存储在第一个条目块中的条目值的第一部分。 每个搜索节点可以包括条目值的一个或多个第二部分。

公开(公告)号：US07545661B2

公开(公告)日：2009-06-09

申请号：US11876118

申请日：2007-10-22

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C7/02 ,  G11C7/18

Abstract: A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of pairs of data lines extend along respective columns of the CAM cells, each pair of data lines including at least one data line that is formed by conductive segments disposed in two different conductivity layers of the CAM device.

Abstract translation: 具有以行和列排列的CAM单元的内容可寻址存储器（CAM）装置。 多对数据线沿着CAM单元的各个列延伸，每对数据线包括由设置在CAM器件的两个不同导电层中的导电段形成的至少一条数据线。

公开(公告)号：US07487200B1

公开(公告)日：2009-02-03

申请号：US09729871

申请日：2000-12-05

Applicant: Varadarajan Srinivasan

Inventor： Varadarajan Srinivasan

IPC: G06F15/16

CPC classification number: G11C8/04 ,  G11C15/04 ,  H03K23/56

Abstract: A digital signal processor. The digital signal processor includes a first data classification block. The first data classification block outputs a first block priority number associated with a first data stored in the first data classification block that matches a search key. The digital signal processor includes a second data classification block. The second data classification block outputs a second priority number associated with a second data stored in the second data classification block that matches the search key. The digital signal processor includes a device index processor. The device index processor selects a most significant block priority number from the first block priority number and the second block priority number.

Abstract translation: 数字信号处理器。 数字信号处理器包括第一数据分类块。 第一数据分类块输出与存储在与搜索关键字匹配的第一数据分类块中的第一数据相关联的第一块优先级编号。 数字信号处理器包括第二数据分类块。 第二数据分类块输出与存储在与搜索关键字匹配的第二数据分类块中的第二数据相关联的第二优先权编号。 数字信号处理器包括设备索引处理器。 设备索引处理器从第一块优先权号码和第二块优先权号码中选择最高有效的块优先权号码。

公开(公告)号：US07461295B1

公开(公告)日：2008-12-02

申请号：US11194067

申请日：2005-07-29

Applicant: Vinay Iyengar ,  Bindiganavale S. Nataraj

Inventor： Vinay Iyengar ,  Bindiganavale S. Nataraj

IPC: G06F11/00

CPC classification number: G01R31/31726 ,  G01R31/3016

Abstract: A method of testing a semiconductor device having a pipelined architecture. Operation of a first pipeline stage of the semiconductor is disabled during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device. A second pipelined operation is executed to enable the second pipeline stage to generate an intermediate result using the test data. A final result of the second pipelined operation is evaluated to determine whether the second pipeline stage produced a correct intermediate result.

Abstract translation: 一种测试具有流水线结构的半导体器件的方法。 在第一流水线操作期间禁用半导体的第一流水线级的操作以在半导体器件的第二流水线级的输入处建立测试数据。 执行第二流水线操作以使得第二流水线级能够使用测试数据生成中间结果。 评估第二流水线操作的最终结果以确定第二流水线阶段是否产生正确的中间结果。

公开(公告)号：US07450409B1

公开(公告)日：2008-11-11

申请号：US11384736

申请日：2006-03-20

Applicant: Dinesh Maheshwari

Inventor： Dinesh Maheshwari

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) device can include a plurality of CAM cells arranged in rows and columns to form multi-byte words. Each CAM cell can include a comparator circuit and one or more data storing circuits. Each comparator circuit can have one or more charge transfer paths arranged between a match line and a first voltage source node. Each data storing circuit can include a write circuit that provides a controllable impedance path between one or more charge transfer paths and a data storage node of the data storing circuit.

Abstract translation: 内容可寻址存储器（CAM）设备可以包括以行和列排列以形成多字节字的多个CAM单元。 每个CAM单元可以包括比较器电路和一个或多个数据存储电路。 每个比较器电路可以具有布置在匹配线和第一电压源节点之间的一个或多个电荷转移路径。 每个数据存储电路可以包括写入电路，其在一个或多个电荷传送路径与数据存储电路的数据存储节点之间提供可控阻抗路径。

公开(公告)号：US07443215B1

公开(公告)日：2008-10-28

申请号：US11938164

申请日：2007-11-09

Applicant: Stefanos Sidiropoulos

Inventor： Stefanos Sidiropoulos

IPC: H03L7/06

CPC classification number: H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract translation: 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。

公开(公告)号：US07432750B1

公开(公告)日：2008-10-07

申请号：US11296786

申请日：2005-12-07

Applicant: Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

Inventor： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

IPC: H03B21/00 ,  H03L7/06

CPC classification number: H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract translation: 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。

公开(公告)号：US07412561B2

公开(公告)日：2008-08-12

申请号：US10801462

申请日：2004-03-15

Applicant: Dimitri C. Argyres ,  Varadarajan Srinivasan

Inventor： Dimitri C. Argyres ,  Varadarajan Srinivasan

IPC: G06F12/00 ,  G11C15/00

CPC classification number: G11C15/00 ,  H04L2012/5685

Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a compound for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.

Abstract translation: 一种在输入数据中相对于输入数据的其他位转置一个或多个位的装置和方法，以形成用于在内容可寻址存储器中搜索的组合。 比较器可以具有从出现在输入数据中的顺序重新排列的一个或多个位，使得来自输入数据的第一段的一个或多个位被来自输入的第二段的一个或多个位替换或替换 数据。

公开(公告)号：US07401180B1

公开(公告)日：2008-07-15

申请号：US10264667

申请日：2002-10-04

Applicant: David V. James ,  Jagadeesan Rajamanickam

Inventor： David V. James ,  Jagadeesan Rajamanickam

IPC: G16F12/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: According to one embodiment, a content addressable memory (CAM) device (100) may include a number of segments (102 or 104). Search target compare circuits (110 and 112) can compare a target value TARGET to programmable information values (PIV0 and PIV1) associated with a particular segment (102 and 104). If a search target value TARGET matches a programmable information value (PIV0 and PIV1), search operations may be performed in a segment (102 or 104). If a search target value TARGET does not match a programmable information value, (PIV0 and PIV1), search operations may be prevented within a segment (102 or 104).

Abstract translation: 根据一个实施例，内容可寻址存储器（CAM）设备（100）可以包括多个段（102或104）。 搜索目标比较电路（110和112）可以将目标值TARGET与与特定段（102和104）相关联的可编程信息值（PIV 0和PIV 1）进行比较。 如果搜索目标值TARGET与可编程信息值（PIV 0和PIV 1）匹配，则可以在段（102或104）中执行搜索操作。 如果搜索目标值TARGET与可编程信息值（PIV 0和PIV 1）不匹配，则可以在段（102或104）内防止搜索操作。

公开(公告)号：US07391200B1

公开(公告)日：2008-06-24

申请号：US11670924

申请日：2007-02-02

Applicant: Sandeep Khanna ,  Varadarajan Srinivasan

Inventor： Sandeep Khanna ,  Varadarajan Srinivasan

IPC: G06F1/18 ,  G05F1/613 ,  H01L29/78 ,  H01L25/00

CPC classification number: H01L27/0921 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An integrated circuit device for delivering power to a load includes a P-MOS power transistor, an N-MOS bypass transistor and a gate driver circuit. The P-MOS power transistor is coupled between a supply voltage node and a power output node of the integrated circuit device, and the N-MOS bypass transistor is coupled between the power output node and a reference node of the integrated circuit device. The gate driver circuit responds to a pulse-width-modulated (PWM) control signal by outputting an active-low drive-enable signal to a gate terminal of the P-MOS power transistor and an active-high bypass-enable signal to a gate terminal of the N-MOS bypass transistor during respective, non-overlapping intervals.

Abstract translation: 用于向负载输送功率的集成电路装置包括P-MOS功率晶体管，N-MOS旁路晶体管和栅极驱动电路。 P-MOS功率晶体管耦合在集成电路器件的电源电压节点和功率输出节点之间，并且N-MOS旁路晶体管耦合在功率输出节点和集成电路器件的参考节点之间。 栅极驱动器电路通过向P-MOS功率晶体管的栅极端子输出有效低驱动使能信号和向栅极施加有效高旁路使能信号来响应脉冲宽度调制（PWM）控制信号 N-MOS旁路晶体管的端子。