公开(公告)号：US20080218919A1

公开(公告)日：2008-09-11

申请号：US12022700

申请日：2008-01-30

Applicant: Philippe Galy ,  Laurent Micheli ,  Ghislain Troussier ,  Mickael Rien ,  Jean-Francois Veniant

Inventor： Philippe Galy ,  Laurent Micheli ,  Ghislain Troussier ,  Mickael Rien ,  Jean-Francois Veniant

IPC: H02H9/00 ,  H01L21/8234

CPC classification number: H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Circuit nodes are identified which, in unpowered mode, can be charged with positive or negative charges but cannot be discharged. Then protective elements are added to allow the discharge of these nodes. These elements do not affect the operation of the circuit in powered mode. Discharges of the two polarities are handled, positive and negative. The circuit is thus more resistant to ESD and passes CDM tests.

Abstract translation: 识别电路节点，其在无电力模式下可以用正电荷或负电荷充电，但不能被放电。 然后添加保护元件以允许这些节点的放电。 这些元件不会影响电源在电源模式下的工作。 处理两极的放电正，负。 因此，该电路更能抵抗ESD并通过CDM测试。

公开(公告)号：US20080212360A1

公开(公告)日：2008-09-04

申请号：US12043766

申请日：2008-03-06

Applicant: Pierre Rizzo ,  Christophe Moreaux ,  David Naura ,  Ahmed Kari

Inventor： Pierre Rizzo ,  Christophe Moreaux ,  David Naura ,  Ahmed Kari

IPC: G11C11/24

CPC classification number: G11C11/4023 ,  G06K7/10029 ,  G06K7/10059 ,  G06K19/07749

Abstract: A persistent volatile memory cell memorizes a binary datum during a retention time independent from a supply voltage of the memory cell. The memory cell comprises a capacitive memory point supplying a persistent voltage and having a determined discharge time, a switch for triggering the discharge of the memory point when an erase signal has an active value, a switch for triggering the charge of the memory point when a write signal has an active value, and a sense-amplifier circuit having an input receiving the persistent voltage, and an output supplying the binary datum. The memory cell can be applied to the management of an inventory flag in a contactless integrated circuit.

Abstract translation: 永久性易失性存储器单元在独立于存储器单元的电源电压的保持时间期间存储二进制数据。 存储单元包括提供持续电压并具有确定的放电时间的电容性存储器点，当擦除信号具有有效值时用于触发存储点放电的开关，当触发存储点的充电时，当a 写信号具有有效值，以及具有接收持续电压的输入的读出放大器电路和提供二进制数据的输出。 存储单元可应用于无接触集成电路中的库存标志的管理。

公开(公告)号：US07421570B2

公开(公告)日：2008-09-02

申请号：US10779855

申请日：2004-02-17

Applicant: Gosagan Padmanabhan ,  Dragos Davidescu ,  Franck Roche

Inventor： Gosagan Padmanabhan ,  Dragos Davidescu ,  Franck Roche

IPC: G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/3004 ,  G06F9/4486 ,  G06F9/461

Abstract: The present invention relates to a method for managing the stack of a microprocessor comprising a central processing unit and a memory array, the central processing unit comprising registers containing contextual data and a stack pointer, the stack being a zone of the memory array used for saving contextual data upon a switch from a first to a second program. According to the present invention, the method comprises saving contextual data contained in a variable number of registers that varies according to the value of at least one flag stored in a register to be saved. Advantages: optimization of the filling of the stack and of the number of subprograms that can be interleaved.

Abstract translation: 本发明涉及一种用于管理包括中央处理单元和存储器阵列的微处理器的堆叠的方法，所述中央处理单元包括包含上下文数据的寄存器和堆栈指针，所述堆栈是用于保存的存储器阵列的区域 从第一程序切换到第二程序时的上下文数据。 根据本发明，该方法包括保存包含在根据存储在要保存的寄存器中的至少一个标志的值而变化的可变数目的寄存器中的上下文数据。 优点：优化堆栈的填充以及可以交错的子程序数量。

公开(公告)号：US20080179750A1

公开(公告)日：2008-07-31

申请号：US12013279

申请日：2008-01-11

Applicant: Vincent Arnal ,  Joaquin Torres

Inventor： Vincent Arnal ,  Joaquin Torres

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76808 ,  H01L21/7682 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated electronic circuit includes superimposed insulating layers and metal elements distributed within said insulating layers. Each insulating layer comprises a first level within which the metal elements lie substantially in the plane of said first level, and a second level traversed by the metal elements in a direction substantially perpendicular to the plane of said second level, so as to come into contact with at least one metal element of the first level. The levels also comprise insulation zones for insulating the metal elements from each other. For at least one insulating layer, at least one of the levels of said at least one insulating layer comprises at least two insulation zones respectively realized of a first material and a second material which are different from each other.

Abstract translation: 集成电子电路包括叠加的绝缘层和分布在所述绝缘层内的金属元​​件。 每个绝缘层包括第一级，其中金属元件基本上位于所述第一级的平面内，第二级由金属元件沿基本上垂直于所述第二级的平面的方向穿过，以便接触 具有至少一个第一级的金属元件。 这些电平还包括用于使金属元件彼此绝缘的绝缘区。 对于至少一个绝缘层，所述至少一个绝缘层的至少一个级别包括分别实现彼此不同的第一材料和第二材料的至少两个绝缘区域。

公开(公告)号：US20080179494A1

公开(公告)日：2008-07-31

申请号：US12006097

申请日：2007-12-28

Applicant: Arnaud Tournier ,  Francois Roy

Inventor： Arnaud Tournier ,  Francois Roy

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14654 ,  H01L27/14601 ,  H01L27/14689

Abstract: A pixel is formed in a semiconductor substrate of a first doping type, a first layer of the second doping type covering the substrate, a second layer of the first doping type covering the first layer. A MOS-type transistor is formed in the second layer and has a drain area and a source area of the second doping type. The pixel includes a first area of the second doping type, more heavily doped than the first layer, crossing the second layer and extending into the first layer and connected to the drain area. The pixel further includes a second area of the first doping type, more heavily doped than the second layer and bordering the source area.

Abstract translation: 像素形成在第一掺杂型的半导体衬底中，覆盖衬底的第二掺杂类型的第一层，覆盖第一层的第一掺杂类型的第二层。 在第二层中形成MOS型晶体管，并具有第二掺杂类型的漏极区域和源极区域。 像素包括第二掺杂类型的第一区域，比第一层更重掺杂，与第二层交叉并延伸到第一层并连接到漏极区域。 像素还包括第一掺杂类型的第二区域，比第二层更重掺杂并且与源极区域接壤。

公开(公告)号：US20080175075A1

公开(公告)日：2008-07-24

申请号：US12016615

申请日：2008-01-18

Applicant: Francesco La Rosa

Inventor： Francesco La Rosa

IPC: G11C7/06

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C16/28

Abstract: A sense amplifier for reading a memory cell, comprising: a read node linked to the memory cell, an active stage connected to the read node and comprising means for supplying a read current on the read node, and a data output linked to a node of the active stage where an electrical voltage representative of the state of conductivity of the memory cell appears. The sense amplifier comprises means for adjusting a voltage appearing on the read node at a value inferior to a value of threshold voltage linked to the manufacturing technique of the sense amplifier. Application in particular to the reading of non-volatile memories of the type EEPROM, FLASH and PCM.

Abstract translation: 一种用于读取存储器单元的读出放大器，包括：链接到存储器单元的读取节点，连接到读取节点的活动阶段，并且包括用于在读取节点上提供读取电流的装置，以及链接到读取节点的节点的数据输出 表示存储单元的电导率状态的电压的活性阶段。 读出放大器包括用于将读出节点上出现的电压调节为低于与读出放大器的制造技术相关联的阈值电压值的值的装置。 特别适用于EEPROM，FLASH和PCM类型的非易失性存储器的读取。

公开(公告)号：US20080169871A1

公开(公告)日：2008-07-17

申请号：US12015093

申请日：2008-01-16

Applicant: Loic Joet

Inventor： Loic Joet

IPC: H03K5/00

CPC classification number: H04B1/16

Abstract: The invention relates to a method for the filtering and analog/digital conversion of an incoming analog signal including an analog filtering of the incoming analog signal so as to filter the frequency components located outside a desired frequency band, and a conversion of the filtered analog signal to a digital signal. The digital signal is reformatted in a form that is substantially similar, at least in the desired frequency band, to the form of the incoming analog signal. A final digital filtering of the reformatted digital signal is performed so as to filter the frequency components located outside the desired frequency band.

Abstract translation: 本发明涉及一种用于滤波和模拟/数字转换输入模拟信号的方法，包括输入模拟信号的模拟滤波，以便对位于期望频带之外的频率分量进行滤波，以及滤波后的模拟信号 到数字信号。 数字信号以至少在所需频带中基本相似的形式重新格式化为输入模拟信号的形式。 执行重新格式化的数字信号的最终数字滤波，以便对位于期望频带之外的频率分量进行滤波。

公开(公告)号：US07400874B2

公开(公告)日：2008-07-15

申请号：US10498681

申请日：2002-12-11

Applicant: Christophe Moreaux ,  Ahmed Kari ,  Olivier Tardieu

Inventor： Christophe Moreaux ,  Ahmed Kari ,  Olivier Tardieu

IPC: H04B1/16

CPC classification number: H03K5/2481 ,  G06F1/04 ,  G06K19/0723 ,  G06K19/073 ,  H03K5/125

Abstract: A contactless integrated circuit receiving an RF signal comprises a clock-signal generator to produce a clock signal from a first half wave and a second half wave representing the received RF signal. Also disclosed is a method for the generation of a clock signal in which the first half wave and the second half wave are compared to produce the clock signal. The invention is adapated for use in contactless cards, transponders, and the like.

Abstract translation: 接收RF信号的非接触式集成电路包括时钟信号发生器，用于产生来自第一半波的时钟信号和表示所接收的RF信号的第二半波。 还公开了一种用于产生其中比较第一半波和第二半波以产生时钟信号的时钟信号的方法。 本发明适用于非接触式卡，转发器等。

公开(公告)号：US07400723B2

公开(公告)日：2008-07-15

申请号：US10467572

申请日：2002-02-06

Applicant: Fabrice Romain ,  Yannick Teglia

Inventor： Fabrice Romain ,  Yannick Teglia

IPC: H04K1/00

CPC classification number: H04L9/0625 ,  G06F2207/7219 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/24

Abstract: A secured method of cryptographic computation to generate output data from input data and from a secret key includes a derived key scheduling step to provide a derived key from the secret key according to a known key scheduling operation. The method also includes a masking step, performed before the derived key scheduling step, to mask the secret key so that the derived scheduled key is different at each implementation of the method. The present method and component can be used in transfer type applications, such as bank type applications.

Abstract translation: 一种用于从输入数据和秘密密钥生成输出数据的密码计算的安全方法包括：派生密钥调度步骤，用于根据已知密钥调度操作，从秘密密钥提供派生密钥。 该方法还包括在导出密钥调度步骤之前执行的掩蔽步骤，以掩蔽该秘密密钥，使得在该方法的每个实现方式上导出的调度密钥不同。 本方法和组件可用于转移类型应用，如银行类型应用。

公开(公告)号：US20080165913A1

公开(公告)日：2008-07-10

申请号：US11971730

申请日：2008-01-09

Applicant: Philippe Roquelaure

Inventor： Philippe Roquelaure

IPC: H03K21/40

CPC classification number: G01R31/318527 ,  G01R31/31719 ,  H03K21/40

Abstract: A method and a circuit for detecting a malfunction of at least one first counter controlled by a first signal, in which a second counter, controlled by a second signal identical to the first signal or to its inverse, and counting in the reverse direction with respect to the first counter, is set with a value complementary to a setting value of the first counter; the respective current values of the first and second counters are added up; and the current sum is compared with at least one value representing the greatest one of the setting values or this greatest value plus one.

Abstract translation: 一种用于检测由第一信号控制的至少一个第一计数器的故障的方法和电路，其中第二计数器由与第一信号相同或相反的第二信号控制，并且相对于 被设置为与第一计数器的设定值互补的值; 第一和第二计数器的相应电流值相加; 并将电流和与表示设定值中最大的一个或该最大值加上一个的至少一个值进行比较。