Input matching circuit for multiband low noise amplifier
    262.
    发明申请
    Input matching circuit for multiband low noise amplifier 失效
    多频低噪声放大器输入匹配电路

    公开(公告)号:US20050225397A1

    公开(公告)日:2005-10-13

    申请号:US11088591

    申请日:2005-03-24

    Abstract: Provided is a multiband low noise amplifier including a first transistor, an input matching circuit, and a first capacitor. The first transistor includes a collector electrically connected to a first power supply, a grounded emitter, and a base connected to the other end of a first inductor having one end as an input end of the low noise amplifier. The input matching circuit is connected between the collector and the base of the first transistor. The first capacitor connected to the collector of the first transistior. The input matching circuit includes a varactor. The input matching circuit includes a second capacitor connected to the varactor. The input matching circuit includes a first resistor connected to the varactor. In the multiband low noise amplifier, a varactor having a variable capacitance is installed at an input end, thereby easily performing band switching through bias voltage control by a small amount and minimizing noises that may be caused by a control signal.

    Abstract translation: 提供了一种包括第一晶体管,输入匹配电路和第一电容器的多频带低噪声放大器。 第一晶体管包括电连接到第一电源,接地发射极和与第一电感器的另一端连接的基极的集电极,第一电感器的一端作为低噪声放大器的输入端。 输入匹配电路连接在第一晶体管的集电极和基极之间。 第一个电容连接到第一个transistior的收集器。 输入匹配电路包括变容二极管。 输入匹配电路包括连接到变容二极管的第二电容器。 输入匹配电路包括连接到变容二极管的第一电阻器。 在多频带低噪声放大器中,具有可变电容的变容二极管安装在输入端,从而通过少量的偏置电压控制容易地执行频带切换并且最小化可能由控制信号引起的噪声。

    Low noise optical amplifier and optical communication system using the same
    263.
    发明授权
    Low noise optical amplifier and optical communication system using the same 失效
    低噪声光放大器和光通信系统使用相同

    公开(公告)号:US06765716B2

    公开(公告)日:2004-07-20

    申请号:US10231266

    申请日:2002-08-30

    CPC classification number: H01S3/06754 H01S3/06758 H01S2301/02

    Abstract: A low noise optical amplifier used in an optical communication system includes optical amplifying elements for amplifying optical signals of a specific wavelength(&lgr;) incident from their ends(F1,F2) and endowing phase difference between ASEs, optical diverging means to interfere the amplified optical signals and the ASEs output from both ends(F1,F2), first path of length(L1) to optically connect the one end(F1) to first gate(D1) of the optical diverging means, and second path of length(L2) to optically connect the other end(F2) to second gate(D2) of the optical diverging means. The first and second paths are designed with distance(L1-L2) so that the amplified optical signal causes reinforcing interference at the third gate(D3) and destructive interference at the fourth gate(D4), and the ASE causes destructive interference at the third gate(D3) and reinforcing interference at fourth gate(D4).

    Abstract translation: 在光通信系统中使用的低噪声光放大器包括用于放大从其端(F1,F2)入射的特定波长(λ)的光信号和ASE之间的赋予相位差的光放大元件,用于干扰放大的光 信号和从两端(F1,F2)输出的长度为(L1)的第一路径,以光学连接光发散装置的一端(F1)到第一门(D1)的ASE,以及长度(L2)的第二路径, 以将另一端(F2)光学地连接到光发散装置的第二栅极(D2)。 第一和第二路径被设计为具有距离(L1-L2),使得放大的光信号在第三栅极(D3)处引起加强干扰并且在第四栅极(D4)处引起相消干涉,并且ASE在第三栅极(D4)处引起相消干涉 门(D3)和第四门(D4)处的加强干涉。

    Parallel test board used in testing semiconductor memory devices
    264.
    发明授权
    Parallel test board used in testing semiconductor memory devices 有权
    用于测试半导体存储器件的并行测试板

    公开(公告)号:US06762615B2

    公开(公告)日:2004-07-13

    申请号:US10094561

    申请日:2002-03-08

    CPC classification number: G11C29/56 G01R1/045 G11C29/48

    Abstract: A parallel test board preferably includes a plurality of serial slots connected to a motherboard and a number of parallel slots connected to the motherboard in parallel with each other. The motherboard provides an actual operational environment for devices under test (DUTs). DUTs are mounted in the slots. Using a plurality of serial slots, distorted timings due to one serial slot (e.g., an extension slot) have an influence on the other serial slot (e.g., a reference slot), as well as on the parallel slots. In this manner, a timing margin failure occurring during a multi-bank operation can be effectively detected. The slots to which the DUTs are mounted preferably have a socket structure with a support block having contact pins arranged thereon. Each of the contact pins preferably has a module contact part configured to contact a tab of the DUT and a board contact part configured to contact conductive wiring patterns of an intermediation board. An elastic member is also preferably interposed between the support block and each of the module and the board contact parts. According to various aspects and embodiments of this invention, testing reliability is improved and the durability of the test board is significantly increased.

    Abstract translation: 平行测试板优选地包括连接到母板的多个串行插槽和与母板并联连接的多个并行插槽。 主板为被测设备(DUT)提供了实际的操作环境。 DUT被安装在插槽中。 使用多个串行时隙,由于一个串行时隙(例如,扩展时隙)引起的失真定时对另一个串行时隙(例如,参考时隙)以及并行时隙产生影响。 以这种方式,可以有效地检测在多行操作期间发生的定时裕度故障。 DUT被安装到的槽优选地具有插座结构,其具有布置在其上的接触针的支撑块。 每个接触针优选地具有被配置为接触DUT的突片的模块接触部分和被配置为接触中介板的导电布线图案的板接触部分。 弹性构件也优选地插入在支撑块和模块和板接触部分中的每一个之间。 根据本发明的各个方面和实施例,提高了测试可靠性,并且显着增加了测试板的耐久性。

    Arrangement of data input/output circuits for use in a semiconductor
memory device
    265.
    发明授权
    Arrangement of data input/output circuits for use in a semiconductor memory device 有权
    用于半导体存储器件中的数据输入/输出电路的布置

    公开(公告)号:US6147924A

    公开(公告)日:2000-11-14

    申请号:US330264

    申请日:1999-06-11

    CPC classification number: G11C5/025

    Abstract: There is provided a semiconductor memory device which includes a plurality of memory cell blocks arranged in rows and columns. Each memory cell block includes a plurality of memory cells for storing data. A plurality of data input/output circuits are divided into a first group and a second group. The first group and the second group are associated with and disposed between a respective subset of the memory cell blocks. The data input/output circuits have a plurality of data input/output pins. A plurality of address signal circuits are arranged between the first group and the second group for receiving externally applied address signals. The semiconductor memory device is packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the data input/output circuits of the first and second groups are collectively arranged adjacent to each other.

    Abstract translation: 提供了一种半导体存储器件,其包括以行和列排列的多个存储单元块。 每个存储单元块包括用于存储数据的多个存储单元。 多个数据输入/输出电路被分成第一组和第二组。 第一组和第二组与存储单元块的相应子集相关联并且被布置在存储单元块的相应子集之间。 数据输入/输出电路具有多个数据输入/输出引脚。 多个地址信号电路被布置在第一组和第二组之间用于接收外部施加的地址信号。 半导体存储器件使用非外部DQ-内部控制(NON-ODIC)型封装进行封装,该封装具有使得第一和第二组的数据输入/输出电路的数据输入/输出引脚集体的结构 彼此相邻布置。

    Computer system having video cassette recorder incorporated therein
    266.
    发明授权
    Computer system having video cassette recorder incorporated therein 失效
    具有并入其中的盒式磁带录像机的计算机系统

    公开(公告)号:US6134376A

    公开(公告)日:2000-10-17

    申请号:US910049

    申请日:1997-08-12

    CPC classification number: H04N5/765 Y10S358/906

    Abstract: A computer system is provided having an internal video cassette recorder incorporated therein in order to provide an effective means of recording/playing a moving picture produced in the computer system onto or from a video cassette usable for camcorders. The computer system include a video cassette recorder having a dimension of a conventional drive to be mounted on the computer case with front panel access, and a VCR control circuit for driving a cassette deck mechanism, as well as reproducing video signals recorded in a video cassette or recording the video signals fed from the computer onto the video cassette; and an interface board installed to connect the cassette recorder VCR with the system bus of the computer and to supply a command signal fed from the computer with the VCR control circuit and to transfer a status signal generated in the VCR circuit to the computer for controlling operation of the VCR.

    Abstract translation: 提供了一种计算机系统,其具有并入其中的内部盒式磁带录像机,以便提供将计算机系统中产生的运动图像记录/播放到可用于摄像机的盒式磁带盒上或从可用于摄像机的盒式磁带录制的有效装置。 计算机系统包括具有要安装在具有前面板存取的计算机机箱上的常规驱动器的尺寸的盒式录像机,以及用于驱动盒式甲板机构的VCR控制电路,以及再现记录在盒式磁带盒中的视频信号 或将从计算机馈送的视频信号记录到录像带上; 以及接口板,用于将盒式磁带录像机VCR与计算机的系统总线连接起来,并将从计算机馈送的命令信号提供给VCR控制电路,并将在VCR电路中生成的状态信号传送到计算机以控制操作 的录像机。

    Refrigerator capable of controlling fan motor
    267.
    发明授权
    Refrigerator capable of controlling fan motor 失效
    冰箱能控制风扇电机

    公开(公告)号:US5983653A

    公开(公告)日:1999-11-16

    申请号:US998276

    申请日:1997-12-24

    Applicant: Chang-Ho Lee

    Inventor: Chang-Ho Lee

    Abstract: A refrigerator capable of controlling a fan motor, in which the fan motor rpm is controlled according to a cooling load, are disclosed. The refrigerator comprises a DC fan motor for operating a cooling fan; a controller for determining cooling load according to inner temperature of the refigerator sensed by thermal sensor and for generating a control signal to select an AC voltage according to the detemined cooling load; a transformer for decreasing an input voltage by several AC voltage levels; a switch for selecting a voltage level output from the transformer according to the control signal from the controller; and a rectifier for converting AC voltage to DC voltage and for supplying the DC voltage to the DC fan motor. According to the above, the rpm of the cooling fan can be varied and controlled easily depending on cooling load of the refrigerator using a DC fan motor.

    Abstract translation: 公开了一种能够控制风扇电动机的冰箱,其中根据冷却负荷来控制风扇电动机转速。 冰箱包括用于操作冷却风扇的DC风扇马达; 控制器,用于根据热传感器检测到的反射器的内部温度来确定冷却负载,并根据确定的冷却负载产生控制信号以选择AC电压; 用于将输入电压降低几个交流电压电平的变压器; 根据来自控制器的控制信号选择从变压器输出的电压电平的开关; 以及用于将AC电压转换为DC电压并将DC电压提供给DC风扇电动机的整流器。 根据上述,可以根据使用DC风扇马达的冰箱的冷却负荷来容易地改变和控制冷却风扇的转速。

    Cam gear for actuating a reel brake mechanism in a video cassette
recorder
    269.
    发明授权
    Cam gear for actuating a reel brake mechanism in a video cassette recorder 失效
    用于致动录像机中的卷轴制动机构的凸轮齿轮

    公开(公告)号:US5713532A

    公开(公告)日:1998-02-03

    申请号:US639415

    申请日:1996-04-29

    Applicant: Chang-Ho Lee

    Inventor: Chang-Ho Lee

    CPC classification number: G11B15/6653 G11B15/22

    Abstract: A cam gear is provided with a camming groove including an inside camming face and an outside camming face. The inside camming face is divided into a stop mode inner-section of a first constant radius, a play mode inner-section of a second constant radius, the second constant radius being larger than the first radius, and a first transition section formed in a manner that an end of the stop mode inner-section is smoothly joined to a beginning of the play mode inner-section. The outside camming face is divided into a stop mode outer-section of a third constant radius, the third constant radius being larger than the first constant radius by a predetermined camming groove width, a play mode outer-section of a fourth constant radius, the fourth constant radius being larger than the second radius by the camming groove width, an intermediate mode outer-section of a fifth constant radius, the fifth constant radius being larger than the third constant radius and being smaller than the fourth constant radius, a second transition section formed in a manner that an end of the stop mode outer-section is smoothly joined to a beginning of the intermediate mode outer-section, and a third transition section formed in a manner that an end of the intermediate mode outer-section is smoothly joined to a beginning of the play mode outer-section.

    Abstract translation: 凸轮齿轮设置有包括内侧凸轮面和外侧凸轮面的凸轮槽。 内侧凸轮面被分为第一恒定半径的停止模式内部部分,第二恒定半径的游戏模式内部部分,第二恒定半径大于第一半径,以及第一过渡部分形成在 使得停止模式内部的端部平滑地接合到播放模式内部的开始的方式。 外侧凸轮面被分为第三恒定半径的停止模式外部部分,第三恒定半径大于第一恒定半径预定的凸轮槽宽度,第四恒定半径的游戏模式外部部分 第四恒定半径大于第二半径的凸轮槽宽度,第五恒定半径的中间模式外部部分,第五恒定半径大于第三恒定半径并且小于第四恒定半径,第二过渡部分 所述截面形成为使得所述止挡模式外侧部分的端部平滑地接合到所述中间模式外部部件的开始端;以及第三过渡部分,其形成为使得所述中间模式外部部分的端部平滑 加入了一个开始的播放模式外部部分。

    Liquid crystal display device
    270.
    发明授权
    Liquid crystal display device 有权
    液晶显示装置

    公开(公告)号:US09396696B2

    公开(公告)日:2016-07-19

    申请号:US12861360

    申请日:2010-08-23

    CPC classification number: G09G5/00 G09G3/36

    Abstract: A liquid crystal display (“LCD”) device includes a display panel, a data driving part, and at least one first light-blocking part and at least one second light-blocking part. The display panel includes a plurality of pixels and a plurality of data lines. The pixels are arranged in a column direction and a row direction. At least one of the data lines extends in a zigzag shape along the column direction to be discontinuously disposed between two adjacent columns of the pixels. The at least one data line is electrically connected to two of the pixels that are adjacent in the row direction. The second light-blocking part is thinner than the first light-blocking part. The first light-blocking part and the second light-blocking are repeatedly disposed on an area between two adjacent columns of the pixels. The data driving part applies a data signal to the data lines.

    Abstract translation: 液晶显示器(“LCD”)器件包括显示面板,数据驱动部分和至少一个第一遮光部分和至少一个第二遮光部分。 显示面板包括多个像素和多条数据线。 像素沿列方向和行方向排列。 数据线中的至少一条沿着列方向以锯齿形延伸,以不连续地设置在像素的两个相邻列之间。 至少一条数据线电连接到在行方向上相邻的两个像素。 第二遮光部分比第一遮光部分薄。 第一遮光部分和第二光阻被重复地设置在像素的两个相邻列之间的区域上。 数据驱动部分将数据信号应用于数据线。

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