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公开(公告)号：US20050225397A1
公开(公告)日：2005-10-13
申请号：US11088591
申请日：2005-03-24
申请人： Rahul Bhatia , Sang-Hyun Woo , Ji-Hoon Bang , Seong-Soo Lee , Chang-Ho Lee , Joy Laskar
发明人： Rahul Bhatia , Sang-Hyun Woo , Ji-Hoon Bang , Seong-Soo Lee , Chang-Ho Lee , Joy Laskar
CPC分类号： H03F3/191 , H03F2200/294 , H03F2200/372 , H03F2203/7209 , H04B1/18
摘要： Provided is a multiband low noise amplifier including a first transistor, an input matching circuit, and a first capacitor. The first transistor includes a collector electrically connected to a first power supply, a grounded emitter, and a base connected to the other end of a first inductor having one end as an input end of the low noise amplifier. The input matching circuit is connected between the collector and the base of the first transistor. The first capacitor connected to the collector of the first transistior. The input matching circuit includes a varactor. The input matching circuit includes a second capacitor connected to the varactor. The input matching circuit includes a first resistor connected to the varactor. In the multiband low noise amplifier, a varactor having a variable capacitance is installed at an input end, thereby easily performing band switching through bias voltage control by a small amount and minimizing noises that may be caused by a control signal.
摘要翻译： 提供了一种包括第一晶体管，输入匹配电路和第一电容器的多频带低噪声放大器。 第一晶体管包括电连接到第一电源，接地发射极和与第一电感器的另一端连接的基极的集电极，第一电感器的一端作为低噪声放大器的输入端。 输入匹配电路连接在第一晶体管的集电极和基极之间。 第一个电容连接到第一个transistior的收集器。 输入匹配电路包括变容二极管。 输入匹配电路包括连接到变容二极管的第二电容器。 输入匹配电路包括连接到变容二极管的第一电阻器。 在多频带低噪声放大器中，具有可变电容的变容二极管安装在输入端，从而通过少量的偏置电压控制容易地执行频带切换并且最小化可能由控制信号引起的噪声。
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公开(公告)号：US07253688B2
公开(公告)日：2007-08-07
申请号：US11088591
申请日：2005-03-24
申请人： Rahul Bhatia , Sang-Hyun Woo , Ji-Hoon Bang , Seong-Soo Lee , Chang-Ho Lee , Joy Laskar
发明人： Rahul Bhatia , Sang-Hyun Woo , Ji-Hoon Bang , Seong-Soo Lee , Chang-Ho Lee , Joy Laskar
CPC分类号： H03F3/191 , H03F2200/294 , H03F2200/372 , H03F2203/7209 , H04B1/18
摘要： Provided is a multiband low noise amplifier including a first transistor, an input matching circuit, and a first capacitor. The first transistor includes a collector electrically connected to a first power supply, a grounded emitter, and a base connected to the other end of a first inductor having one end as an input end of the low noise amplifier. The input matching circuit is connected between the collector and the base of the first transistor. The first capacitor connected to the collector of the first transistior. The input matching circuit includes a varactor. The input matching circuit includes a second capacitor connected to the varactor. The input matching circuit includes a first resistor connected to the varactor. In the multiband low noise amplifier, a varactor having a variable capacitance is installed at an input end, thereby easily performing band switching through bias voltage control by a small amount and minimizing noises that may be caused by a control signal.
摘要翻译： 提供了一种包括第一晶体管，输入匹配电路和第一电容器的多频带低噪声放大器。 第一晶体管包括电连接到第一电源，接地发射极和与第一电感器的另一端连接的基极的集电极，第一电感器的一端作为低噪声放大器的输入端。 输入匹配电路连接在第一晶体管的集电极和基极之间。 第一个电容连接到第一个transistior的收集器。 输入匹配电路包括变容二极管。 输入匹配电路包括连接到变容二极管的第二电容器。 输入匹配电路包括连接到变容二极管的第一电阻器。 在多频带低噪声放大器中，具有可变电容的变容二极管安装在输入端，从而通过少量的偏置电压控制容易地执行频带切换并且最小化可能由控制信号引起的噪声。
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公开(公告)号：US20090193238A1
公开(公告)日：2009-07-30
申请号：US12153409
申请日：2008-05-19
申请人： Ji-Hoon Bang , Kwang-Chul Kim
发明人： Ji-Hoon Bang , Kwang-Chul Kim
IPC分类号： G06F9/30
CPC分类号： G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided. The multi-mode providing apparatus includes: at least one reconfigurable operation mode execution unit performing a plurality of operations for processing a predetermined operation mode; a common coarse-grained array unit shared temporally by the at least one reconfigurable operation mode execution unit, and performing a main processing operation set to be performed by the common coarse-grained array unit, among the plurality of operations; and a controller determining whether the common coarse-grained array unit is available, and according to the result of the determination controlling the at least one reconfigurable operation mode execution unit so that the common coarse-grained array unit or an exclusive coarse-grained array unit performs the main processing operation, the exclusive coarse-grained array unit included in the at least one reconfigurable operation mode execution unit. Therefore, it is possible to reduce a delay time for data processing while reducing the size of hardware.
摘要翻译： 提供了可重构处理器（RP）结构，特别地，提供了包括用于每种模式的排他粗粒度阵列单元和多模式提供方法的多模式提供装置。 多模式提供装置包括：执行用于处理预定操作模式的多个操作的至少一个可重构操作模式执行单元; 由所述至少一个可重构操作模式执行单元在时间上共享的公共粗粒度阵列单元，并且在所述多个操作中执行由所述公共粗粒度阵列单元执行的主处理操作; 以及控制器，确定所述公共粗粒子阵列单元是否可用，并且根据所述确定的结果控制所述至少一个可重构操作模式执行单元，使得所述公共粗粒度阵列单元或排他粗粒度阵列单元 执行主处理操作，包括在至少一个可重构操作模式执行单元中的排他的粗粒度阵列单元。 因此，可以减少数据处理的延迟时间，同时减小硬件的尺寸。
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公开(公告)号：US07870364B2
公开(公告)日：2011-01-11
申请号：US12153409
申请日：2008-05-19
申请人： Ji-Hoon Bang , Kwang-Chul Kim
发明人： Ji-Hoon Bang , Kwang-Chul Kim
CPC分类号： G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided. The multi-mode providing apparatus includes: at least one reconfigurable operation mode execution unit performing a plurality of operations for processing a predetermined operation mode; a common coarse-grained array unit shared temporally by the at least one reconfigurable operation mode execution unit, and performing a main processing operation set to be performed by the common coarse-grained array unit, among the plurality of operations; and a controller determining whether the common coarse-grained array unit is available, and according to the result of the determination controlling the at least one reconfigurable operation mode execution unit so that the common coarse-grained array unit or an exclusive coarse-grained array unit performs the main processing operation, the exclusive coarse-grained array unit included in the at least one reconfigurable operation mode execution unit. Therefore, it is possible to reduce a delay time for data processing while reducing the size of hardware.
摘要翻译： 提供了可重构处理器（RP）结构，特别地，提供了包括用于每种模式的排他粗粒度阵列单元和多模式提供方法的多模式提供装置。 多模式提供装置包括：执行用于处理预定操作模式的多个操作的至少一个可重构操作模式执行单元; 由所述至少一个可重构操作模式执行单元在时间上共享的公共粗粒度阵列单元，并且在所述多个操作中执行由所述公共粗粒度阵列单元执行的主处理操作; 以及控制器，确定所述公共粗粒子阵列单元是否可用，并且根据所述确定的结果控制所述至少一个可重构操作模式执行单元，使得所述公共粗粒度阵列单元或排他粗粒度阵列单元 执行主处理操作，包括在至少一个可重构操作模式执行单元中的排他的粗粒度阵列单元。 因此，可以减少数据处理的延迟时间，同时减小硬件的尺寸。
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