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公开(公告)号：US11482487B2
公开(公告)日：2022-10-25
申请号：US17064119
申请日：2020-10-06
Inventor： David Auchere , Claire Laporte , Deborah Cogoni , Laurent Schwartz
Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.
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公开(公告)号：US20220197644A1
公开(公告)日：2022-06-23
申请号：US17644718
申请日：2021-12-16
Inventor： Diana Moisuc , Christophe Eichwald
Abstract: Method for detecting the linear extraction of information in a processor using an instruction register for storing an instruction includes an operation code. The method includes monitoring the instructions successively stored in the instruction register including decoding the operation codes, determining the number of consecutive operation codes encoding incremental branches, and generating a detection signal if the number is greater than or equal to a detection threshold.
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公开(公告)号：US20220181316A1
公开(公告)日：2022-06-09
申请号：US17457203
申请日：2021-12-01
Applicant: STMICROELECTRONICS SA , STMicroelectronics (Alps) SAS
Inventor： Jeremie Forest , Vincent Knopik , Laurent Schwartz
IPC: H01L27/02 , H01L23/552
Abstract: Electronic chip comprising a first integrated circuit, a second integrated circuit, a first link connecting the first integrated circuit and the second integrated circuit, a second link connecting the first integrated circuit and the second integrated circuit, a surface-mount component, the component being configured and placed to limit an electromagnetic disturbance by the first link of the second link.
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公开(公告)号：US20220069430A1
公开(公告)日：2022-03-03
申请号：US17408982
申请日：2021-08-23
Applicant: STMicroelectronics (Alps) SAS
Inventor： Deborah COGONI
Abstract: An electronic device includes a first layer with an antenna and a second metal layer that extends over the entire first layer. The second metal layer includes at least one laterally-closed cavity that is located vertically above the antenna. The cavity is filled, at least in part, by a resin material. A first plate supporting a second metal plate extends over the cavity with the second metal plate positioned vertically above the antenna. The first metal plate may be supported by a ledge within the cavity. Alternatively, the second metal plate is embedded in the resin filling the cavity, with the second metal plate positioned vertically above the antenna.
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公开(公告)号：US20210366865A1
公开(公告)日：2021-11-25
申请号：US17396346
申请日：2021-08-06
Inventor： Romain COFFY , Patrick LAURENT , Laurent SCHWARTZ
Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.
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Patent Agency Ranking
公开(公告)号：US20210273664A1
公开(公告)日：2021-09-02
申请号：US17187024
申请日：2021-02-26
Applicant: STMicroelectronics (Alps) SAS
Inventor： Frederic Rivoirard , Felix Gauthier
Abstract: An embodiment integrated electronic device comprises a mixer module including a voltage/current transconductor stage including first transistors and connected to a mixing stage including second transistors, wherein the mixing stage includes a resistive degeneration circuit connected to the sources of the second transistors and a calibration input connected to the gates of the second transistors and intended to receive an adjustable calibration voltage, and the sources of the first transistors are directly connected to a cold power supply point.
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公开(公告)号：US20210266024A1
公开(公告)日：2021-08-26
申请号：US17180751
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.
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公开(公告)号：US20210265950A1
公开(公告)日：2021-08-26
申请号：US17180752
申请日：2021-02-20
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS
Abstract: The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.
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269.发明申请公开(公告)号：US20210203152A1
公开(公告)日：2021-07-01
申请号：US17202566
申请日：2021-03-16
Applicant: STMicroelectronics (Alps) SAS
Inventor： Frederic Lebon , Laurent Chevalier
Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.
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公开(公告)号：US20210160193A1
公开(公告)日：2021-05-27
申请号：US17100505
申请日：2020-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
Inventor： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC: H04L12/933 , H04L12/24
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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