公开(公告)号：US20220181316A1

公开(公告)日：2022-06-09

申请号：US17457203

申请日：2021-12-01

Applicant: STMICROELECTRONICS SA ,  STMicroelectronics (Alps) SAS

Inventor： Jeremie Forest ,  Vincent Knopik ,  Laurent Schwartz

IPC: H01L27/02 ,  H01L23/552

Abstract: Electronic chip comprising a first integrated circuit, a second integrated circuit, a first link connecting the first integrated circuit and the second integrated circuit, a second link connecting the first integrated circuit and the second integrated circuit, a surface-mount component, the component being configured and placed to limit an electromagnetic disturbance by the first link of the second link.

公开(公告)号：US11482487B2

公开(公告)日：2022-10-25

申请号：US17064119

申请日：2020-10-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Claire Laporte ,  Deborah Cogoni ,  Laurent Schwartz

IPC: H01L23/50 ,  H01L23/31

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

公开(公告)号：US11756874B2

公开(公告)日：2023-09-12

申请号：US17945822

申请日：2022-09-15

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Claire Laporte ,  Deborah Cogoni ,  Laurent Schwartz

IPC: H01L23/50 ,  H01L23/31

CPC classification number: H01L23/50 ,  H01L23/315 ,  H01L23/3128

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

公开(公告)号：US12051681B2

公开(公告)日：2024-07-30

申请号：US17374868

申请日：2021-07-13

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Deborah Cogoni ,  David Auchere ,  Laurent Schwartz ,  Claire Laporte

IPC: H01L25/16 ,  H01G4/38

CPC classification number: H01L25/165 ,  H01G4/385

Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.

公开(公告)号：US11676928B2

公开(公告)日：2023-06-13

申请号：US17396346

申请日：2021-08-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Romain Coffy ,  Patrick Laurent ,  Laurent Schwartz

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/24 ,  H01L21/56 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/16 ,  H01L24/73 ,  H01L24/82 ,  H01L2224/0233 ,  H01L2224/02315 ,  H01L2224/02381 ,  H01L2224/16145 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82048 ,  H01L2224/82108

Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

公开(公告)号：US11114404B2

公开(公告)日：2021-09-07

申请号：US16704082

申请日：2019-12-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Romain Coffy ,  Patrick Laurent ,  Laurent Schwartz

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.