公开(公告)号：US10298260B2

公开(公告)日：2019-05-21

申请号：US15553908

申请日：2016-02-23

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Jae-Young Lee ,  Heung-Mook Kim

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/27 ,  H03M13/29 ,  H03M13/15 ,  H03M13/25

Abstract: A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

公开(公告)号：US10256839B2

公开(公告)日：2019-04-09

申请号：US15641084

申请日：2017-07-03

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Heung-Mook Kim ,  Sun-Hyoung Kwon ,  Nam-Ho Hur

IPC: H03M13/25 ,  H04L1/00 ,  H03M13/11 ,  H03M13/00 ,  H03M13/03

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

公开(公告)号：US10224964B2

公开(公告)日：2019-03-05

申请号：US15426940

申请日：2017-02-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Bo-Mi Lim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/27 ,  H04L1/00 ,  H03M13/17

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

公开(公告)号：US10212012B2

公开(公告)日：2019-02-19

申请号：US15766153

申请日：2016-11-01

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung-Ik Park ,  Jae-Young Lee ,  Sun-Hyoung Kwon ,  Heung-Mook Kim

IPC: H04L27/26 ,  H04J11/00 ,  H04W4/06 ,  H04L1/00 ,  H04L27/34 ,  H04N21/2343 ,  H04N19/30

Abstract: An apparatus and method for generating a broadcast signal frame including preamble for signaling injection level information. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes an injection level controller configured to generate a power reduced enhanced layer signal by reducing a power of an enhanced layer signal; a combiner configured to generate a multiplexed signal by combining a core layer signal and the power reduced enhanced layer signal; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling injection level information corresponding to the injection level controller.

公开(公告)号：US10177866B2

公开(公告)日：2019-01-08

申请号：US15323944

申请日：2015-07-03

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  R&DB FOUNDATION, KOREA MARITIME AND OCEAN UNIVERSITY

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Jeong-Chang Kim ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: H04H20/42 ,  H04L27/26 ,  H04L1/00 ,  H04J11/00 ,  H04L27/34 ,  H04L29/08

Abstract: A broadcast signal transmission apparatus and method using layered division multiplexing are disclosed. A broadcast signal transmission apparatus according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; a frame builder configured to generate a broadcast signal frame using the time-interleaved signal; and an orthogonal frequency division multiplexing (OFDM) transmitter configured to generate a pilot signal that is shared by a core layer corresponding to the core layer signal and an enhanced layer corresponding to the enhanced layer signal.

公开(公告)号：US10177788B2

公开(公告)日：2019-01-08

申请号：US15644455

申请日：2017-07-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Heung-Mook Kim ,  Sun-Hyoung Kwon ,  Nam-Ho Hur

IPC: H03M13/11 ,  H04L1/00 ,  H03M13/00 ,  H03M13/25

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 2/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

公开(公告)号：US10142152B2

公开(公告)日：2018-11-27

申请号：US15556243

申请日：2016-03-04

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung-Ik Park ,  Jae-Young Lee ,  Sun-Hyoung Kwon ,  Heung-Mook Kim

IPC: H04L1/00 ,  H04L29/06 ,  H04L27/26

Abstract: An apparatus and method for broadcast signal frame using a bootstrap and a preamble are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a time interleaver configured to generate a time-interleaved signal by performing interleaving on a BICM output signal; and a frame builder configured to generate a broadcast signal frame including a bootstrap and a preamble using the time-interleaved signal.

公开(公告)号：US10110250B2

公开(公告)日：2018-10-23

申请号：US15346004

申请日：2016-11-08

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung-Ik Park ,  Heung-Mook Kim ,  Sun-Hyoung Kwon ,  Nam-Ho Hur

IPC: H03M13/11 ,  H03M13/00 ,  H04L1/00 ,  G06F11/10

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

公开(公告)号：US09941902B2

公开(公告)日：2018-04-10

申请号：US15642199

申请日：2017-07-05

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Sung-Ik Park ,  Heung-Mook Kim ,  Sun-Hyoung Kwon ,  Nam-Ho Hur

IPC: H03M13/11 ,  H04L1/00 ,  H03M13/25 ,  H03M13/00

CPC classification number: H03M13/1185 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/116 ,  H03M13/1165 ,  H03M13/255 ,  H03M13/616 ,  H04L1/0041 ,  H04L1/0043 ,  H04L1/0057 ,  H04L1/0065

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

公开(公告)号：US09806744B2

公开(公告)日：2017-10-31

申请号：US15374609

申请日：2016-12-09

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung-Ik Park ,  Sun-Hyoung Kwon ,  Jae-Young Lee ,  Heung-Mook Kim ,  Nam-Ho Hur

IPC: G06F11/00 ,  H03M13/27 ,  H03M13/11 ,  H03M13/00

CPC classification number: H03M13/2792 ,  G06F11/1076 ,  H03M13/1102 ,  H03M13/1151 ,  H03M13/1165 ,  H03M13/255 ,  H03M13/2739 ,  H03M13/2778 ,  H03M13/6552

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.