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    Interposer monitor coupled to clock, start, enable of monitor trigger
    272.
    发明授权
    Interposer monitor coupled to clock, start, enable of monitor trigger 有权
    内置显示器耦合到时钟，启动，启用监视器触发

    公开(公告)号：US09261558B2

    公开(公告)日：2016-02-16

    申请号：US14505948

    申请日：2014-10-03

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/3185

    CPC classification number: G01R31/2884 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536

    Abstract: The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.

    Abstract translation: 本公开描述了一种用于改进插入器以包括用于实时监视位于插入器中的数字信号，模拟信号，电压信号和温度传感器的嵌入式监视仪器的新型方法和装置。 嵌入式监视器触发单元控制实时监控操作的启动和停止。 嵌入式监控仪器可通过插入器上的1149.1 TAP接口访问。

    DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS
    274.
    发明申请
    DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS 审中-公开
    双模式测试访问端口方法和设备

    公开(公告)号：US20160033572A1

    公开(公告)日：2016-02-04

    申请号：US14879299

    申请日：2015-10-09

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318572 ,  G06F1/10

    Abstract: An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a register capture state output, and a register update state output. Register circuitry has a test data in lead input, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead. Selection circuitry has an input connected to the serial data input lead, an input connected to a test pattern source lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead.

    Abstract translation: 集成电路具有耦合到测试时钟和测试模式选择输入的控制器电路，并且具有状态寄存器时钟状态输出，寄存器捕获状态输出和寄存器更新状态输出。 寄存器电路具有引线输入中的测试数据，耦合到控制器电路的状态输出的控制输入和控制输出。 连接电路具有连接到寄存器电路的控制输出的控制输入，并且将第一扫描电路的第一串行数据输出和第二扫描电路的第二串行数据输出之一选择性地耦合到测试数据输出。 选择电路具有连接到串行数据输入引线的输入端，连接到测试图案源极引线的输入端，耦合到扫描电路控制输出引线的控制输入端以及连接到扫描输入引线的输出端。

    IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES
    275.
    发明申请
    IEEE 1149.1 AND P1500 TEST INTERFACES COMBINED CIRCUITS AND PROCESSES 审中-公开
    IEEE 1149.1和P1500测试接口组合电路和过程

    公开(公告)号：US20150377963A1

    公开(公告)日：2015-12-31

    申请号：US14849832

    申请日：2015-09-10

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  H03K19/0175

    CPC classification number: G01R31/31713 ,  G01R31/28 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318594 ,  G06F1/12 ,  G06F13/287 ,  G06F13/4282 ,  H03K19/017509

    Abstract: In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

    Abstract translation: 在第一实施例中，允许IEEE标准1149.1的测试访问端口（TAP）从IEEE标准P1500的包装器串行端口（WSP）命令控制，使得通常由WSP控制的P1500架构被TAP控制 。 在第二实施例（1）中，基于TAP和WSP的架构被合并在一起，使得先前描述的架构元件的共享是可能的，并且（2）TAP和WSP测试接口被合并到单个优化的测试接口中，该接口是可操作的 执行每个单独测试界面的所有操作。 一种方法提供了TAP来保持对TAP指令寄存器的访问和控制，但提供了一个选择的数据寄存器，由TAP + ATC（辅助测试控制总线）或离散的CaptureDR，UpdateDR，TransferDR访问和控制 ，ShiftDR和ClockDR WSP数据寄存器控制信号。

    DIRECT SCAN ACCESS JTAG
    276.
    发明申请
    DIRECT SCAN ACCESS JTAG 审中-公开
    直接扫描访问JTAG

    公开(公告)号：US20150369863A1

    公开(公告)日：2015-12-24

    申请号：US14837786

    申请日：2015-08-27

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177

    CPC classification number: G01R31/318558 ,  G01R31/2851 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318572 ,  G01R31/318594

    Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

    Abstract translation: 本公开描述了用于直接访问存在于许多串行连接的JTAG Tap域的扫描路径中的JTAG Tap域的新颖的方法和装置。 由JTAG控制器直接扫描访问所选的Tap域，可以使用与Tap域关联并连接到JTAG控制器的辅助数字或模拟终端。 在直接扫描访问期间，辅助数字或模拟端子用作所选Tap域与JTAG控制器之间的串行数据输入和串行数据输出路径。

    METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL
    278.
    发明申请
    METHOD AND APPARATUS FOR TEST CONNECTIVITY, COMMUNICATION, AND CONTROL 审中-公开
    用于测试连接，通信和控制的方法和装置

    公开(公告)号：US20150331046A1

    公开(公告)日：2015-11-19

    申请号：US14809936

    申请日：2015-07-27

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/318544 ,  G01R31/31855 ,  G01R31/318555 ,  G01R31/318575

    Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.

    Abstract translation: 功能电路和电路核心使用扫描路径在集成电路上进行测试。 为这些扫描路径使用并行扫描分配器和集电极电路可以改善IC内部电路和内核的测试访问，并降低了扫描测试期间的IC功耗。 用于分配器和集电极电路的控制器包括测试控制寄存器，测试控制状态机和多路复用器。 这些测试电路可以以层次结构或并行连接。 传统的测试访问端口或TAP可以被修改为与公开的测试电路一起工作。

    SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
    280.
    发明申请
    SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT 审中-公开
    可选择的JTAG或跟踪数据存储和输出

    公开(公告)号：US20150323598A1

    公开(公告)日：2015-11-12

    申请号：US14802685

    申请日：2015-07-17

    Applicant: Texas Instruments Incorporated

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177

    CPC classification number: G01R31/31723 ,  G01R31/31722 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318572 ,  G06F11/261 ,  G06F11/267 ,  G06F11/27 ,  G06F11/3466

    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

    Abstract translation: 地址和命令端口接口选择性地启用IC内的JTAG TAP域操作和跟踪域操作。 端口在单个引脚上承载TMS和TDI输入和TDO输出，并在单独的引脚上接收时钟信号。 可寻址的两个引脚接口将指令和数据加载并更新到IC内的TAP域。 多个IC中的指令或数据更新操作同时发生。 过程使用数据帧将数据从寻址的目标设备发送到控制器，每个数据帧包括报头位和数据位。 标头位的逻辑电平用于启动，继续和停止向控制器传输数据。 控制器和多个目标设备之间的数据和时钟信号接口提供每个目标设备被单独寻址并命令执行JTAG或跟踪操作。

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