公开(公告)号：US10998000B2

公开(公告)日：2021-05-04

申请号：US16733624

申请日：2020-01-03

Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA

Inventor： Hiroshi Yahata ,  Tadamasa Toma

IPC: G11B20/10 ,  G11B27/32 ,  H04N5/85 ,  G11B27/10 ,  H04N9/804 ,  H04N9/82 ,  H04N5/93 ,  H04N9/87

Abstract: A recording medium includes a video stream of a standard-luminance range and a video stream of high-luminance range, which are used selectively in accordance with a playback environment. The recording medium also includes a subtitle stream of the standard-luminance range and a subtitle stream of the high-luminance range, which are used selectively in accordance with the playback environment. A playlist file includes a management region where playback control information relating to a main stream is stored, and includes an extended region. The management region stores first playback control information specifying playing of the video stream of the high-luminance range and the subtitle stream of the high-luminance range in combination. The extended region stores second playback control information specifying playing of the video stream of the standard-luminance range and the subtitle stream of the standard-luminance range in combination.

公开(公告)号：US10992898B2

公开(公告)日：2021-04-27

申请号：US16575729

申请日：2019-09-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masayuki Kozuka ,  Takashi Higashida ,  Yoshihiro Mori ,  Haruyasu Hirakawa ,  Tadamasa Toma

IPC: H04N5/57 ,  H04N11/24 ,  H04N21/435 ,  H04N21/431 ,  H04N5/20 ,  H04N9/64

Abstract: Provided is a display method of displaying, on a display device, video of video data where luminance of video is defined by a first EOTF corresponding to HDR. The method includes: acquiring the video data; performing first conversion where the luminance of the video is converted to a luminance corresponding to a dynamic range of a third EOTF, where, with regard to a second EOTF that is part of the first EOTF and is the part of a luminance range where the peak luminance indicated by the peak luminance information included in the acquired video data is maximum luminance, the dynamic range of luminance of the second EOTF is reduced with maximum luminance of the second EOTF matching displayable luminance of the display device, while maintaining the relative relationship of luminance of the second EOTF; and displaying the video on the display device using the result of the first conversion.

公开(公告)号：US20210120291A1

公开(公告)日：2021-04-22

申请号：US17134877

申请日：2020-12-28

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Noritaka Iguchi ,  Tadamasa Toma ,  Takahiro Nishi ,  Hisaya Katou

IPC: H04N21/242 ,  H04N21/44 ,  H04H60/13 ,  H04N21/43 ,  H04N21/462 ,  H04N21/61 ,  H04N21/8547

Abstract: According to one aspect of the present disclosure, a reception method in broadcast and broadband cooperation service, the reception method includes: receiving broadcast content transmitted through broadcast; receiving acquisition information through the broadcast, the acquisition information being information used to play back broadband content transmitted through broadband while the broadband content is synchronized with the received broadcast content, the acquisition information being information relating to acquisition of the broadband content; and acquiring the broadband content based on the received acquisition information. Therefore, the broadband content can properly be acquired in response to the reception of the broadcast content.

公开(公告)号：US10972754B2

公开(公告)日：2021-04-06

申请号：US16388339

申请日：2019-04-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Chong Soon Lim ,  Han Boon Teo ,  Ru Ling Liao ,  Jing Ya Li ,  Sughosh Pavan Shashidhar ,  Hai Wei Sun

IPC: H04N19/176 ,  H04N19/119 ,  H04N19/60 ,  H04N19/18 ,  H04N19/124

Abstract: An encoder includes: circuitry; and memory. Using the memory, the circuitry: performs, when a size of a current block to be subjected to transform processing is not a power of 2, complementary processing of adding a complementary region to the current block to cause the size to be a power of 2; performs transform processing on the current block which has been subjected to the complementary processing; performs inverse transform processing on the current block which has been subjected to the transform processing; and eliminates the complementary region included in the current block which has been subjected to the inverse transform processing.

公开(公告)号：US10951896B2

公开(公告)日：2021-03-16

申请号：US16269018

申请日：2019-02-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Takashi Hashimoto ,  Tadamasa Toma

IPC: H04N19/13 ,  H04N19/157 ,  H04N19/91 ,  H04N19/18

Abstract: An encoder includes memory and circuitry accessible to the memory. The circuitry accessible to the memory: switches whether or not to apply arithmetic encoding to a binary data string in which image information has been binarized; binarizes frequency transform coefficient information according to different binarization formats between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string; and binarizes a part or the entirety of prediction parameter information according to a binarization format which is common between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string.

公开(公告)号：US10939114B2

公开(公告)日：2021-03-02

申请号：US15931917

申请日：2020-05-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/13 ,  H04N19/184 ,  H04L29/06 ,  H04N19/70 ,  H04N19/176

Abstract: An encoder includes memory and circuitry which: (i) encodes an image block; (ii) when encoding the image block: binarizes coefficient information indicating coefficients of the image block; and controls whether to apply arithmetic encoding to a binary data string obtained by binarizing the coefficient information; and (iii) when binarizing the coefficient information: binarizes the coefficient information according to a first syntax structure when arithmetic encoding is applied to the data string and a predetermined condition is not satisfied; binarizes the coefficient information according to a second syntax structure when arithmetic encoding is applied to the data string and the predetermined condition is satisfied; binarizes the coefficient information according to the second syntax structure when no arithmetic encoding is applied to the data string; and subtracts 1 from a value of an initial non-zero coefficient when no arithmetic encoding is applied to the data string when encoding the image block.

公开(公告)号：US10904527B2

公开(公告)日：2021-01-26

申请号：US16911834

申请日：2020-06-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Takashi Hashimoto ,  Tadamasa Toma

IPC: H04N19/122 ,  H04N19/13 ,  H04N19/146 ,  H04N19/176 ,  H04N19/18 ,  H04N19/61 ,  H04N19/136 ,  H04N19/124 ,  H04N19/159

Abstract: An encoder which encodes image information includes memory and circuitry accessible to the memory. The circuitry binarizes a data value indicating the number of non-zero coefficients included in a current basic block which is one of one or more basic blocks in a frequency transform block, according to a conversion table, to encode the image information which includes the data value. When binarizing the data value, the circuitry selects the conversion table from a plurality of tables including two or more tables which differ from each other in difference between a longest bit length and a shortest bit length of a plurality of binary values associated with a plurality of data values, according to the position of the current basic block in the current frequency transform block which is the frequency transform block including the current basic block, and binarizes the data value according to the conversion table selected.

公开(公告)号：US10863175B2

公开(公告)日：2020-12-08

申请号：US16287252

申请日：2019-02-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/119 ,  H04N19/176 ,  H04N19/107 ,  H04N19/46

Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: writes, into a bitstream, one or more parameters including a first parameter indicating that a first partition of an image is to be split into a plurality of partitions including at least a second partition which is a non-rectangular partition; splits the first partition, based on the first parameter; and encodes at least the second partition.

公开(公告)号：US10819985B2

公开(公告)日：2020-10-27

申请号：US16684012

申请日：2019-11-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

Abstract: An encoder includes memory, and circuitry accessible to the memory. The circuitry accessible to the memory: determines whether OBMC is applicable to generation of a prediction image of a current block, according to whether BIO is to be applied to the generation of the prediction image of the current block; when BIO is to be applied to the generation of the prediction image of the current block, determines that OBMC is not applicable to the generation of the prediction image of the current block, and applies BIO to the generation of the prediction image of the current block without applying OBMC.

公开(公告)号：US10812827B2

公开(公告)日：2020-10-20

申请号：US16407550

申请日：2019-05-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh

IPC: H04N19/119 ,  H04N19/593 ,  H04N19/44 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: prohibits a first splitting method when arrangement and shapes of blocks obtained by splitting a first block multiple times by the first splitting method are identical to arrangement and shapes of blocks obtained by splitting the first block multiple times by a second splitting method different from the first splitting method, and when scan order of the blocks obtained by the first splitting method is identical to scan order of the blocks obtained by the second splitting method; and encodes the first block.