Method and apparatus for frequency and timing distribution through a packet-based network
    21.
    发明申请
    Method and apparatus for frequency and timing distribution through a packet-based network 有权
    通过基于分组的网络进行频率和时序分配的方法和装置

    公开(公告)号:US20030137997A1

    公开(公告)日:2003-07-24

    申请号:US10132086

    申请日:2002-04-24

    发明人: Pierce V. Keating

    IPC分类号: H04J003/06

    CPC分类号: H04J3/0667

    摘要: A reference frequency is distributed through a packet-based network to remote elements in a system. Timing packets are periodically sent from a master timing element, to be received by at least one peripheral timing element. Echo messages are sent to the master timing element by each peripheral timing element after a unique delay, in response to the reception of a timing packet. Loopback delay measurements are included in each timing packet for each peripheral timing element. Each peripheral timing element locks a loop using only timing packets which incur a minimum loopback delay.

    摘要翻译: 参考频率通过基于分组的网络分发到系统中的远程元件。 定时分组从主定时元件周期性地发送,由至少一个外围定时元件接收。 响应于定时分组的接收,回波消息由唯一延迟之后的每个外围定时元件发送到主定时元件。 环路延迟测量包括在每个周期定时元件的每个定时分组中。 每个外围定时元件仅使用产生最小环回延迟的定时分组来锁定循环。

    Digital undersampling
    22.
    发明授权
    Digital undersampling 有权
    数字欠采样

    公开(公告)号:US07474712B1

    公开(公告)日:2009-01-06

    申请号:US10749799

    申请日:2003-12-30

    申请人: Pierce Keating

    发明人: Pierce Keating

    IPC分类号: H04L24/00

    CPC分类号: H03M1/1255 H04L27/2338

    摘要: A method and system for processing a signal are disclosed. The method comprises: applying an algorithm to selectively negate a plurality of samples of the signal to provide negated and non-negated samples of the signal, and use the negated and non-negated samples as in-phase (I) and/or quadrature (Q) components of a plurality of complex samples, the algorithm being such that the plurality of complex samples are equivalent to the result that would be obtained by applying an effective sampling function to the signal, and selecting a beat frequency of the effective sampling function by adjusting the algorithm.

    摘要翻译: 公开了一种用于处理信号的方法和系统。 该方法包括:应用一种算法来选择性地取消信号的多个样本以提供信号的否定和非否定采样,并将否定和非否定采样用作同相(I)和/或正交( Q)多个复数样本的分量,所述算法使得所述多个复样本等于通过对所述信号应用有效采样函数而获得的结果,并且通过以下方式选择所述有效采样函数的拍频 调整算法。

    Transporting GSM packets over a discontinuous IP Based network
    23.
    发明申请
    Transporting GSM packets over a discontinuous IP Based network 失效
    通过不连续的基于IP的网络传输GSM数据包

    公开(公告)号:US20080285478A1

    公开(公告)日:2008-11-20

    申请号:US12152469

    申请日:2008-05-14

    IPC分类号: H04L12/26

    摘要: A system for transferring data includes an interface configured to receive data that is sent via a first link, and a processor coupled to the interface. The processor is configured to: receive data that is sent via a first link; determine whether there is discontinuity in the received data, the determination being based at least in part on information included in the received data; in the event that the received data includes a discontinuity, generate replacement data that repairs the discontinuity; and transmit at least a portion of replacement data to a second link such that a synchronization requirement associated with the second link is fulfilled.

    摘要翻译: 用于传送数据的系统包括被配置为接收经由第一链路发送的数据的接口和耦合到该接口的处理器。 处理器被配置为:接收经由第一链路发送的数据; 确定所接收的数据是否存在不连续性,所述确定至少部分地基于包括在所接收的数据中的信息; 在接收到的数据包括不连续性的情况下,生成修复不连续性的替换数据; 并将至少一部分替换数据发送到第二链路,使得满足与第二链路相关联的同步要求。

    Clock oscillator
    27.
    发明申请
    Clock oscillator 有权
    时钟振荡器

    公开(公告)号:US20060109058A1

    公开(公告)日:2006-05-25

    申请号:US11255094

    申请日:2005-10-19

    申请人: Pierce Keating

    发明人: Pierce Keating

    IPC分类号: H03L7/085

    CPC分类号: H03K3/03 H03K3/014

    摘要: An oscillator circuit and a method of generating an oscillating signal are disclosed. An oscillator comprises a first flip-flop and a second flip-flop coupled with the first flip-flop to provide an oscillating signal. A method of generating an oscillating signal comprises providing the oscillating signal as a first clock input to a first flip flop, inverting the oscillating signal and providing the inverted oscillating signal as a second clock input to a second flip flop, using the output of the first flip flop and the output of the second flip flop to generate a combined output that alternates between a logic low level and a logic high level, and using the combined output to sustain the oscillation of the oscillating signal.

    摘要翻译: 公开了振荡电路和产生振荡信号的方法。 振荡器包括与第一触发器耦合以提供振荡信号的第一触发器和第二触发器。 一种产生振荡信号的方法包括:提供振荡信号作为第一触发器的第一时钟输入,反相振荡信号,并将反相振荡信号提供给第二触发器的第二时钟输入,使用第一触发器的输出 触发器和第二触发器的输出以产生在逻辑低电平和逻辑高电平之间交替的组合输出,并且使用组合输出来维持振荡信号的振荡。

    Clock oscillator
    28.
    发明授权
    Clock oscillator 失效
    时钟振荡器

    公开(公告)号:US06975174B1

    公开(公告)日:2005-12-13

    申请号:US10749798

    申请日:2003-12-30

    申请人: Pierce Keating

    发明人: Pierce Keating

    IPC分类号: H03D13/00 H03K3/014 H03K3/03

    CPC分类号: H03K3/03 H03K3/014

    摘要: An oscillator circuit and a method of generating an oscillating signal are disclosed. An oscillator comprises a first flip-flop and a second flip-flop coupled with the first flip-flop to provide an oscillating signal. A method of generating an oscillating signal comprises providing the oscillating signal as a first clock input to a first flip flop, inverting the oscillating signal and providing the inverted oscillating signal as a second clock input to a second flip flop, using the output of the first flip flop and the output of the second flip flop to generate a combined output that alternates between a logic low level and a logic high level, and using the combined output to sustain the oscillation of the oscillating signal.

    摘要翻译: 公开了振荡电路和产生振荡信号的方法。 振荡器包括与第一触发器耦合以提供振荡信号的第一触发器和第二触发器。 一种产生振荡信号的方法包括:提供振荡信号作为第一触发器的第一时钟输入,反相振荡信号,并将反相振荡信号提供给第二触发器的第二时钟输入,使用第一触发器的输出 触发器和第二触发器的输出以产生在逻辑低电平和逻辑高电平之间交替的组合输出,并且使用组合输出来维持振荡信号的振荡。

    Network delay control
    29.
    发明申请
    Network delay control 有权
    网络延迟控制

    公开(公告)号:US20050226156A1

    公开(公告)日:2005-10-13

    申请号:US11054345

    申请日:2005-02-08

    IPC分类号: H04L12/26 H04L29/06 H04L29/08

    摘要: Controlling the flow of network traffic to avoid undesired delay in the transmission of timing sensitive packets is disclosed. A plurality of packets to be transmitted via a network transmission path is monitored. A time at which a timing sensitive packet will become available for transmission via the network transmission path is anticipated. The plurality of packets is controlled in light of the anticipated time so that packets other than the timing sensitive packet will not occupy the network transmission path at a time associated with the anticipated time. Approximating a maximum data transmission rate associated with a network transmission path by sending and analyzing receipt of a series of test packets is disclosed. Approximating a buffer size of a buffer associated with a network transmission path by sending and analyzing receipt of a series of test packets is disclosed.

    摘要翻译: 公开了控制网络流量的流量以避免定时敏感分组的传输中的不希望的延迟。 监视经由网络传输路径发送的多个分组。 期望时间敏感分组将可用于经由网络传输路径传输的时间。 根据预期时间来控制多个分组,使得除了定时敏感分组之外的分组在与预期时间相关联的时间不占用网络传输路径。 公开了通过发送和分析一系列测试分组的接收来近似与网络传输路径相关联的最大数据传输速率。 公开了通过发送和分析一系列测试分组的接收来近似与网络传输路径相关联的缓冲器的缓冲器大小。

    PLL with phase clipping and resynchronization
    30.
    发明授权
    PLL with phase clipping and resynchronization 有权
    PLL具有相位限幅和重新同步

    公开(公告)号:US07508274B2

    公开(公告)日:2009-03-24

    申请号:US11441266

    申请日:2006-05-25

    申请人: Pierce Keating

    发明人: Pierce Keating

    IPC分类号: H03L7/085

    摘要: A phase locked loop with phase clipping and/or resynchronization is disclosed. A reference signal is compared to a feedback signal derived at least in part from an output signal of an oscillator to determine a phase error. A magnitude of at least one of the phase error and a change in the phase error, if required, is clipped to provide at least one of a clipped phase error that has a clipped magnitude that does not exceed a prescribed maximum phase error and a clipped change in phase error that has a clipped magnitude that does not exceed a prescribed maximum change in phase error. If a resynchronization triggering event is detected, the oscillator is resynchronized with the reference signal.

    摘要翻译: 公开了一种具有相位限幅和/或再同步的锁相环。 将参考信号与至少部分地从振荡器的输出信号导出的反馈信号进行比较,以确定相位误差。 如果需要,相位误差和相位误差的变化中的至少一个的幅度被限制,以提供具有不超过规定的最大相位误差的限制幅度和限幅的相位误差中的至少一个 具有不超过规定的相位误差最大变化的限幅幅度的相位误差的变化。 如果检测到重新同步触发事件,则振荡器与参考信号重新同步。