公开(公告)号：USD723494S1

公开(公告)日：2015-03-03

申请号：US29457407

申请日：2013-06-10

Applicant: SpectraLink Corporation

Designer： Simon Skafdrup ,  Klaus Lauritsen ,  Ole Madsbøll

公开(公告)号：US5794163A

公开(公告)日：1998-08-11

申请号：US482895

申请日：1995-06-07

Applicant: Graeme S. Paterson ,  Gary L. Bliss ,  Mark R. Boyd

Inventor： Graeme S. Paterson ,  Gary L. Bliss ,  Mark R. Boyd

IPC: H04B1/38 ,  H04M1/60 ,  H04Q7/32

CPC classification number: H04M1/6058 ,  H04B1/38

Abstract: A wireless telephone using an RF receiver unit and an RF transmitter unit and having a removable headset, the telephone and headset particularly suitable for applications where the RF transmitter unit is switched on and off at a frequency less than twenty kilohertz. The wireless telephone is coupled to the headset using a conventional stereo plug and jack. A headset detect logic signal is generated from the speaker audio line. A microphone current detect logic signal is generated from the microphone audio line. A digital logic circuit, preferably including a microprocessor, monitors the headset detect logic signal and microphone current detect logic signals and generates a programmed response to the headset detect logic signal. The programmed response reduces audible noise to the headset user, generates a ringing signal on the speaker audio line when an incoming call is received and allows the headset user to answer incoming calls, and place outgoing calls while touching only the headset. The wireless telephone and headset include circuitry to reject RF noise and circuitry to attenuate RF noise passed into the wireless telephone by a long multi-conductor wire coupling the headset to the wireless telephone.

公开(公告)号：US5334952A

公开(公告)日：1994-08-02

申请号：US38147

申请日：1993-03-29

Applicant: Steven L. Maddy ,  Graeme S. Paterson

Inventor： Steven L. Maddy ,  Graeme S. Paterson

IPC: H03L7/189 ,  H03L7/199 ,  H03L7/08 ,  H03L7/085 ,  H03L7/10 ,  H03L7/16

CPC classification number: H03L7/189 ,  H03L7/199

Abstract: A phase locked loop including a switch between a phase detector output and a VCO input to open the PLL during a frequency change is provided. While the PLL is open, an analog error correction signal is generated by sampling any residual error coming from the phase detector, and generating the analog error correction signal to counter the residual error. Once analog error correction signal is available, the switch is closed and the error correction signal is added to the phase detector output and the PLL is allowed to settle to an optimized frequency.

Abstract translation: 提供了一种锁相环，其包括在频率变化期间在相位检测器输出和VCO输入之间切换以打开PLL的开关。 当PLL打开时，通过对来自相位检测器的任何残余误差进行采样，产生模拟错误校正信号，并产生模拟误差校正信号以抵消残余误差。 一旦模拟错误纠正信号可用，开关闭合，纠错信号加到相位检测器输出端，允许PLL稳定到最佳频率。

公开(公告)号：US5177766A

公开(公告)日：1993-01-05

申请号：US709600

申请日：1991-06-03

Applicant: Bruce M. Holland ,  Gary L. Bliss

Inventor： Bruce M. Holland ,  Gary L. Bliss

IPC: H04B1/707

CPC classification number: H04B1/707

Abstract: A unique method and system is disclosed for generating digital clock timing in a receiver for use in direct-sequence spread-spectrum digital communication systems wherein spread data is delivered from a transmitter to a receiver. The present invention provides at the transmitter frames of digital communication data with each frame having a plurality of time slots and with each time slot having a plurality of digital bits. The transmitter utilizes direct-sequence spreading codes for spreading the digital bits in the time frame. The direct sequence spreading codes each have the same fixed sequence length of M chips and, furthermore, the number of chips per bit CB to spread each digital bit is constant and fully aligned with each digital bit. The ration of M:CB is an integer and the ratio of time of each time slot to the time of the M chips also equals an integer. The spread frames of digital information are despread at the receiver with receiver provided identical direct-sequence codes. The digital clock timing is generated from the receiver's pseudo random sequence generator. Bit timing equals CB*8, nibble timing equals 4*CB, and byte timing equals CB.

Abstract translation: 公开了用于在接收机中产生数字时钟定时的独特方法和系统，用于直接序列扩频数字通信系统，其中扩展数据从发射机传送到接收机。 本发明在数字通信数据的发射机帧中提供每个帧具有多个时隙，并且每个时隙具有多个数字比特。 发射机利用直接序列扩展码在时间帧内扩展数字比特。 直接序列扩展码各自具有相同的M个码片的固定序列长度，此外，扩展每个数字比特的每比特CB的码片数是恒定的并且与每个数字比特完全对齐。 M：CB的比例是整数，每个时隙的时间与M个码片的时间的比率也等于一个整数。 数字信息的扩展帧在接收机处被解扩，接收机提供相同的直接序列码。 从接收机的伪随机序列发生器产生数字时钟定时。 位定时等于CB * 8，半字节定时等于4 * CB，字节定时等于CB。