Abstract:
A CMOS image sensor and method the same are disclosed. The method comprises forming an insulating interlayer including a plurality of photodiodes on a semiconductor substrate, forming a plurality of metal lines within the insulating interlayer, sequentially forming an oxide layer and a passivation layer on the insulating interlayer, forming a TEOS layer on the passivation layer, forming a planarization layer on a portion of the TEOS layer, and forming a microlens on the planarization layer.
Abstract:
A semiconductor device having a test pattern for measuring epitaxial pattern shift is provided. The test pattern includes a semiconductor substrate having a first pattern formed therein; a first impurity region formed in the semiconductor substrate; an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a second pattern formed therein, wherein the second pattern corresponds to the first pattern; and a second impurity region formed in the epitaxial layer, the second impurity region in electrical contact with the first impurity region.
Abstract:
Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, ions of low concentration may be implanted into a photodiode region of a semiconductor substrate to form a photodiode. At least one gate insulating layer pattern may be formed on the semiconductor substrate, and a gate electrode may be formed on each of the at least one gate insulating layer pattern to receive charges from the photodiode. Spacers may be formed at sidewalls of the gate electrode, respectively. A selective epitaxial growth layer may be formed on the photodiode, and ions of low concentration may be obliquely implanted into one side and the other side of the gate electrode to form a low concentration source and a low concentration drain extending below the spacer. Subsequently, a high concentration source and a high concentration drain may be formed on both sides of the gate electrode, respectively.
Abstract:
Provided is a semiconductor device including a metal dummy pattern and a thin film resistor. In detail, a semiconductor device includes a semiconductor substrate, a thin film resistor, and a metal dummy pattern. The thin film resistor disposed over the semiconductor substrate and extending in a first direction relative to the semiconductor substrate. The metal dummy pattern disposed between the semiconductor substrate and the thin film resistor, the metal dummy pattern including a reflective pattern extending in the first direction semiconductor substrate and spatially corresponding to a periphery of the thin film resistor.
Abstract:
Provided is a home-network UMB system and a method thereof for providing interoperability between devices connected one another through different types of middlewares in a home network. The home-network UMB system includes: a bridge core for establishing/releasing a connection between bridge adaptors of different types of middlewares and analyzing/transferring a universal middleware message in order to interoperate devices connected through different types of middlewares existed on a home network; and a plurality of bridge adaptor for connecting the bridge core to a corresponding middleware, and finding/releasing different types of devices, controlling/monitoring different types of devices and registering/creating an event for different types of devices through transforming a universal middleware bridge message to a local message of each middleware and vice versa.
Abstract:
An image sensor includes first to fourth image sensing sections symmetrically aligned in a form of a 2×2 matrix, first to fourth pixel arrays aligned in the first to fourth image sensing sections, respectively, in adjacent to each other, and first to fourth peripheral circuit parts aligned at peripheral portions of the first to fourth image sensing sections. A middle-size CMOS image sensor is provided that is suitable for the available field size of conventional photo equipment, so the manufacturing cost may be minimized and price competitiveness may be maximized while providing high-quality images with high pixel resolution.
Abstract:
An integrated gateway apparatus includes a policy storage for storing therein a first information on message filtering and switching policies for messages received from heterogeneous devices in lower networks via network interfaces; a device management unit for extracting a second information on the messages, the devices and the network interfaces; a layer-basis filter unit for performing, based on the first and the second information, the message filtering and switching on the messages on a layer basis; and an integrated switch management unit for providing the first information to the layer-basis filter unit and controlling the layer-basis filtering unit. The layer-basis filter unit includes a switch filter unit, a route filter unit and a gateway filter unit for performing the message filtering and switching in a MAC layer, in a network layer and a transport layer and in an application layer, respectively.
Abstract:
Provided are an apparatus and a method for searching/managing a home network service based on a home network condition. The apparatus, includes: a service storing unit for storing a home network service; a device information analyzing unit for analyzing home network device information and checking a type of the home network device information; a service searching unit for searching a related home network service list according to the type of the home network device information in the home network service list; and a service operation managing unit for installing the home network service upon installation request of the user in the list of the searched home network service, and managing an operation of the home network service upon operation request of the user in the list of the installed home network service.
Abstract:
An image sensor includes a semiconductor substrate; a pixel array disposed on the semiconductor substrate; and an insulating interlayer, formed on the semiconductor substrate, having a trench coinciding with the disposition of the pixel array, the trench having uniformly inclined inner sidewalls.
Abstract:
A method for fabricating a transistor of semiconductor is disclosed. A disclosed method comprises: forming an STI structure and a well region in a silicon substrate; forming a first dummy gate electrode including spacers and a first gate oxide layer on the well region; forming source and drain regions including an LDD structure around the first dummy gate electrode by using the first dummy gate electrode and the spacers as a ion implantation mask, and performing a thermal treatment; removing the first dummy gate electrode and the first gate oxide layer under the first dummy gate electrode; forming a second dummy gate electrode and a second gate oxide layer; forming a thin nitride layer and a PMD on the silicon substrate including the second dummy gate electrode; performing a CMP process for the thin nitride layer and the PMD until the top of the spacers is exposed; removing the second dummy gate electrode and the second gate oxide layer; forming a third gate oxide layer and polysilicon for a gate electrode; performing another CMP process until the top of the spacers is exposed; and additionally etching the upper portion of the gate electrode.