公开(公告)号：US20100141324A1

公开(公告)日：2010-06-10

申请号：US12330768

申请日：2008-12-09

Applicant: Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

IPC: H03L5/00

CPC classification number: H03K19/018521

Abstract: An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.

Abstract translation: 输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。 高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。 动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。 焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。 本文公开了混合电压输入/输出（I / O）缓冲器。

公开(公告)号：US20100097117A1

公开(公告)日：2010-04-22

申请号：US12289132

申请日：2008-10-21

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC: H03L5/00

CPC classification number: H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

Abstract: A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.

Abstract translation: 混合电压输入/输出（I / O）缓冲器包括输出缓冲电路。 输出缓冲电路包括输出级电路，栅极跟踪电路和浮动N阱电路。 输出级电路包括堆叠上拉P型晶体管和堆叠式下拉式N型晶体管，其中堆叠上拉P型晶体管的第一P型晶体管和第一N型晶体管 堆叠的下拉式N型晶体管耦合到I / O焊盘。 栅极跟踪电路根据I / O焊盘的电压来控制第一P型晶体管的栅极电压，以防止漏电流。 浮动N阱电路为第一P型晶体管的N阱和第二P型晶体管的N阱提供N阱电压，控制栅极的第一P型晶体管的栅极电压 跟踪电路，以防止漏电流。

公开(公告)号：US20090066367A1

公开(公告)日：2009-03-12

申请号：US12184271

申请日：2008-08-01

Applicant: Chua-Chin Wang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

Inventor： Chua-Chin Wang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC: H03K19/0175

CPC classification number: H03K19/00315

Abstract: An input output device coupled between a core circuit and a pad and including an output cell, an input cell, and a pre-driver. The output cell includes an output stage and a voltage level converter. The output stage includes a first transistor and a second transistor connected to the first transistor in serial between a first supply voltage and a second voltage. The voltage level converter generates a first gate voltage to the first transistor according to the first voltage and a data signal. When the first supply voltage is increased, the first gate voltage is increased. When the data signal is at a high level, the first transistor is turned on. The input cell includes a pull unit and a first N-type transistor. The pre-driver turns off the first and the second transistors.

Abstract translation: 耦合在核心电路和焊盘之间并包括输出单元，输入单元和预驱动器的输入输出设备。 输出单元包括输出级和电压电平转换器。 输出级包括在第一电源电压和第二电压之间串联连接到第一晶体管的第一晶体管和第二晶体管。 电压电平转换器根据第一电压和数据信号产生到第一晶体管的第一栅极电压。 当第一电源电压增加时，第一栅极电压增加。 当数据信号处于高电平时，第一晶体管导通。 输入单元包括拉单元和第一N型晶体管。 预驱动器关闭第一和第二晶体管。

公开(公告)号：US08658098B2

公开(公告)日：2014-02-25

申请号：US13548788

申请日：2012-07-13

Applicant: I-Yu Huang ,  Yu-Cheng Lin ,  Chua-Chin Wang ,  Ying-Chung Chen

Inventor： I-Yu Huang ,  Yu-Cheng Lin ,  Chua-Chin Wang ,  Ying-Chung Chen

IPC: G01N27/00

CPC classification number: G01N33/54373

Abstract: A portable detection system for allergic diseases includes a filtration-based inspection module and a reader module. The filtration-based inspection module includes an FPW sensor and a liquid sample filtration apparatus, wherein the liquid sample filtration apparatus includes an injection opening, a passage module, a filtering membrane and a gathering aperture. The injection opening is in communication with the gathering aperture. The FPW sensor comprises a frame body, a carrier and a sensing chip having an accommodating slot in communication with the gathering aperture. The carrier comprises a plurality of conductive terminals, and the conductive terminals are electrically connected with the sensing chip. The reader module comprises a connection slot capable of being inserted by the conductive terminals of the carrier.

Abstract translation: 用于过敏性疾病的便携式检测系统包括基于过滤的检查模块和读取器模块。 基于过滤的检查模块包括FPW传感器和液体样品过滤装置，其中液体样品过滤装置包括注射开口，通道模块，过滤膜和聚集孔。 注射开口与收集孔连通。 FPW传感器包括框架体，载体和具有与收集孔连通的容纳槽的感测芯片。 载体包括多个导电端子，并且导电端子与感测芯片电连接。 读取器模块包括能够被载体的导电端子插入的连接槽。

公开(公告)号：US20130057992A1

公开(公告)日：2013-03-07

申请号：US13589285

申请日：2012-08-20

Applicant: Federico A. Altolaguirre ,  Ming-Dou Ker ,  Chua-Chin Wang

Inventor： Federico A. Altolaguirre ,  Ming-Dou Ker ,  Chua-Chin Wang

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.

Abstract translation: 具有泄漏电流降低功能的ESD保护电路包括可控硅整流器，第一CMOS反相器，第一晶体管，电流镜，PMOS电容器和电阻器。 第一个CMOS反相器与可控硅整流器电连接。 第一晶体管包括第一端，第二端和第三端，其中第一端与可控硅整流器和第一CMOS反相器电连接，并且电流镜与第一晶体管的第三端电连接。 PMOS电容器与电流镜电连接，并且电阻器与第一CMOS反相器，第一晶体管的第二端和PMOS电容器电连接。

公开(公告)号：US08212590B2

公开(公告)日：2012-07-03

申请号：US13067598

申请日：2011-06-13

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC: H03B1/00

CPC classification number: H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

Abstract: A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.

Abstract translation: 混合电压I / O缓冲器包括输入缓冲电路。 输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。 第一反相器反相输入信号以产生第一控制信号。 第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。 第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。 输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。 当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。

公开(公告)号：US20110298498A1

公开(公告)日：2011-12-08

申请号：US12845297

申请日：2010-07-28

Applicant: Chua-Chin WANG ,  Ron-Chi KUO ,  Jen-Wei LIU ,  Ming-Dou KER

Inventor： Chua-Chin WANG ,  Ron-Chi KUO ,  Jen-Wei LIU ,  Ming-Dou KER

IPC: H03K5/22

CPC classification number: G01R31/2621

Abstract: A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage.

Abstract translation: 角检测器包括PMOS阈值电压检测器和NMOS阈值电压检测器，PMOS阈值电压检测器由第一时钟端子，第一CMOS反相器，第一电容器，PMOS阈值电压函数发生器和第一电压输出端子 ，其中所述PMOS阈值电压函数发生器电连接到所述第一电容器并施加以产生作为阈值电压的函数的电压信号的第一公式，所述NMOS阈值电压检测器由第二时钟端子，第二CMOS反相器， 第二电容器，NMOS阈值电压函数发生器和第二电压输出端子，其中所述NMOS阈值电压函数发生器电连接到所述第二电容器并且被施加以产生作为阈值电压的函数的电压信号的第二公式。

公开(公告)号：US07868659B2

公开(公告)日：2011-01-11

申请号：US12575787

申请日：2009-10-08

Applicant: Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

Inventor： Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

IPC: H03K19/0175

CPC classification number: H03K19/018592 ,  H03K3/0375 ,  H03K3/356113 ,  H03K19/00315 ,  H03K19/018521

Abstract: The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.

Abstract translation: 本发明涉及一种具有两倍于电源电压容限的I / O缓冲器，其使用正常的电源电压器件。 本发明的I / O缓冲器包括驱动器，第一电平转换器，门控电路和动态源输出级。 I / O缓冲器的信号分为第一电压范围和第二电压范围。 第一个电压范围为正常电源电压为零，第二个电压范围为正常电源电压的两倍于电源电压。 因此，I / O缓冲器中任何一个晶体管的任何两个端子之间的电压不会超过正常电源电压，因此本发明的I / O缓冲器可以以两倍的电压摆幅发送和接收信号 正常电源电压采用正常供电电压器件，无栅氧化可靠性问题。

公开(公告)号：US20100277216A1

公开(公告)日：2010-11-04

申请号：US12835202

申请日：2010-07-13

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC: H03L5/00

CPC classification number: H03K19/018521 ,  H03K19/018528

Abstract: An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.

Abstract translation: 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。

公开(公告)号：US20100253392A1

公开(公告)日：2010-10-07

申请号：US12575787

申请日：2009-10-08

Applicant: Ming-Dou KER ,  Yan-Liang Lin ,  Chua-Chin Wang

Inventor： Ming-Dou KER ,  Yan-Liang Lin ,  Chua-Chin Wang

IPC: H03B1/00

CPC classification number: H03K19/018592 ,  H03K3/0375 ,  H03K3/356113 ,  H03K19/00315 ,  H03K19/018521

Abstract: The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.

Abstract translation: 本发明涉及一种具有两倍于电源电压容限的I / O缓冲器，其使用正常的电源电压器件。 本发明的I / O缓冲器包括驱动器，第一电平转换器，门控电路和动态源输出级。 I / O缓冲器的信号分为第一电压范围和第二电压范围。 第一个电压范围为正常电源电压为零，第二个电压范围为正常电源电压的两倍于电源电压。 因此，I / O缓冲器中任何一个晶体管的任何两个端子之间的电压不会超过正常的电源电压，因此本发明的I / O缓冲器可以以两倍的电压摆幅发送和接收信号 正常电源电压采用正常供电电压器件，无栅氧化可靠性问题。