Abstract:
A torsion spring tester incorporates a microprocessor based data acquisition/control package and special tooling. The tooling makes calibration of the tester very easy. The combination of the tooling and control package permits acquisition, storage and transfer of test data that is accurate, absolute and repeatable.
Abstract:
The transducer diaphragm includes a folded sheet of thin film material, having a front surface and having a plurality of rearwardly extending projections in the form of fins or vanes thereon. Each one of the projections has at least one conductor portion disposed thereon. A substantially flat, thin sheet is secured to form the front face of the diaphragm and to help rigidify the folded sheet. In the preferred form of the invention, each one of the projections is generally channel-shaped throughout its length, and has a bight portion interconnecting a pair of leg portions. In one form of the invention, at least one portion of a conductor is disposed on each one of the projections. The diaphragm is made from a blank, which includes the sheet of film material having a pair of similar conductors, each configured in a similar manner and deposited on the opposite sides thereof in an oppositely disposed confronting relationship and in registration with one another, so that the blank can be readily folded to form the diaphragm, without causing it to bow or otherwise be deformed.
Abstract:
Dynamic control of memory affinity is provided for a shared memory logical partition within a shared memory partition data processing system having a plurality of nodes. The memory affinity control approach includes: determining one or more home node assignments for the shared memory logical partition, with each assigned home node being one node of the plurality of nodes of the system; determining a desired physical page level per node for the shared memory logical partition; and allowing the shared memory partition to run and using the home node assignment(s) and its desired physical page level(s) in the dispatching of tasks to physical processors in the nodes and in hypervisor page memory management to dynamically control memory affinity of the shared memory logical partition in the data processing system.
Abstract:
Relocating data in a virtualized environment maintained by a hypervisor administering access to memory with a Cache Page Table (‘CPT’) and a Physical Page Table (‘PPT’), the CPT and PPT including virtual to physical mappings. Relocating data includes converting the virtual to physical mappings of the CPT to virtual to logical mappings; establishing a Logical Memory Block (‘LMB’) relocation tracker that includes logical addresses of an LMB, source physical addresses of the LMB, target physical addresses of the LMB, a translation block indicator for each relocation granule, and a pin count associated with each relocation granule; establishing a PPT entry tracker including PPT entries corresponding to the LMB to be relocated; relocating the LMB in a number of relocation granules including blocking translations to the relocation granules during relocation; and removing the logical addresses from the LMB relocation tracker.
Abstract:
A system, method, and computer-usable medium for probing hypervisor tasks in an asynchronous environment. According to an embodiment of the invention, the partition firmware sends a request for data to the hypervisor. When the hypervisor receives the request for data, the hypervisor returns a taskID that identifies the task allocated to handle the request. Partition firmware records the taskID and a timestamp, which indicates the time in which the hypervisor received the request. A timer is set to measure the amount of time elapsed since the task ID was received by a requesting partition firmware. If the hypervisor has not provided the partition firmware with the requested data after a predetermined time period measured by the timer has elapsed, the partition firmware inquires about the status of the task associated with the taskID. If the task is still running, the partition firmware returns control of the partition to the operating system.
Abstract:
In response to a hypervisor page fault for memory that is not resident in a shared memory pool, an I/O paging request is sent to an external storage paging space. In response to a paging service partition encountering an I/O paging error, a paging failure indication is sent to the hypervisor. A simulated machine check interrupt instruction is sent from the hypervisor to the shared memory partition and a machine check handler obtains control. The machine check handler performs data analysis utilizing an error log in an attempt to isolate the I/O paging error to a process or a set of processes in the shared memory partition. The process or set of processes associated with the I/O paging error, or the shared memory partition itself, may be terminated. Finally, the shared memory partition may clear or initialize the page associated with the I/O paging error.
Abstract:
Dynamic control of memory affinity is provided for a shared memory logical partition within a shared memory partition data processing system having a plurality of nodes. The memory affinity control approach includes: determining one or more home node assignments for the shared memory logical partition, with each assigned home node being one node of the plurality of nodes of the system; determining a desired physical page level per node for the shared memory logical partition; and allowing the shared memory partition to run and using the home node assignment(s) and its desired physical page level(s) in the dispatching of tasks to physical processors in the nodes and in hypervisor page memory management to dynamically control memory affinity of the shared memory logical partition in the data processing system.
Abstract:
Methods, apparatus, and products are disclosed for controlling an operational mode for a logical partition on a computing system that include: receiving, in a hypervisor installed on the computing system, a processor compatibility mode for the logical partition and a firmware compatibility mode for the logical partition, the processor compatibility mode specifying a processor architecture version configured for the logical partition, and the firmware compatibility mode specifying a firmware architecture version configured for the logical partition; providing, by the hypervisor for the logical partition, a firmware interface in dependence upon the firmware compatibility mode; and providing, by the hypervisor for the logical partition, a processor interface in dependence upon the processor compatibility mode.
Abstract:
A torsion tester incorporates a microprocessor based data acquisition/control package and special tooling. The tooling makes calibration of the tester very easy. The combination of the tooling and control package permits acquisition, storage and transfer of test data that is accurate, absolute and repeatable. In addition, torsion tester provides a zeroing pin and a zeroing slot on opposing tooling members for calibration. Further, the torsion tester provides an interchangably mounted load cell.
Abstract:
A system to utilize a non-deterministic shared local bus to transport signals to and from TDM signal channels via processing devices that use a pseudo clock signal derived from local bus transfers to synchronize those data transfers with the highly accurate clock of the TDM bus.