公开(公告)号：US09229884B2

公开(公告)日：2016-01-05

申请号：US13460287

申请日：2012-04-30

Applicant: Bryan D. Marietta ,  Gary L. Whisenhunt ,  Kumar K. Gala ,  David B. Kramer

Inventor： Bryan D. Marietta ,  Gary L. Whisenhunt ,  Kumar K. Gala ,  David B. Kramer

IPC: G06F13/24 ,  G06F13/14

CPC classification number: G06F13/14

Abstract: A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g., 14, 61) by executing a control instruction (47, 48) to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register (25) at a physical address (PA) retrieved from a special purpose register (46) so that the partitioned device (14, 61) can determine if the access command can be performed based on local access control information.

Abstract translation: 用于数据处理系统的方法和电路通过执行控制指令（47,48）来提供用于访问分区设备（例如，14,61）的虚拟化指令，以将数据有效载荷中的访问命令（CMD）编码和存储在 硬件插入分区属性（LPID），用于存储到从专用寄存器（46）检索的物理地址（PA）处的命令寄存器（25），使得分区设备（14,61）可以确定访问命令是否可以 基于本地访问控制信息执行。

公开(公告)号：US08914550B2

公开(公告)日：2014-12-16

申请号：US13841916

申请日：2013-03-15

Applicant: Tommi M. Jokinen ,  David B. Kramer ,  Kum Xu

Inventor： Tommi M. Jokinen ,  David B. Kramer ,  Kum Xu

IPC: G06F3/00 ,  G06F13/00 ,  G06F5/00 ,  G06F13/12

CPC classification number: G06F13/126

Abstract: A data processing device includes a plurality of devices, a processor core, a memory, and a queue manager. The processor core stores one or more commands in a command queue of the memory to be executed by the plurality of devices to implement a data transfer path. The queue manager stores a frame queue for each of the plurality of devices. Each frame queue includes a first field having a pointer to an address of the command queue, and a second field to identify a next-in-sequence frame queue. A first device stores a data descriptor in the frame queue of the second device to initiate a data transfer from the first device to the second device. The data descriptor includes a field to indicate an offset value from the address of the command queue to a location of a command to be executed by the second device.

Abstract translation: 数据处理设备包括多个设备，处理器核心，存储器和队列管理器。 处理器核心将一个或多个命令存储在由多个设备执行的存储器的命令队列中以实现数据传输路径。 队列管理器存储多个设备中的每一个的帧队列。 每个帧队列包括具有指向命令队列的地址的指针的第一字段和用于标识下一个序列帧队列的第二字段。 第一设备将数据描述符存储在第二设备的帧队列中，以启动从第一设备到第二设备的数据传输。 数据描述符包括用于指示从命令队列的地址到由第二设备执行的命令的位置的偏移值的字段。

公开(公告)号：US20140219276A1

公开(公告)日：2014-08-07

申请号：US13760109

申请日：2013-02-06

Applicant: Tommi M. Jokinen ,  David B. Kramer ,  Kun Xu

Inventor： Tommi M. Jokinen ,  David B. Kramer ,  Kun Xu

IPC: H04L12/56

CPC classification number: H04L47/62

Abstract: A source processor can divide each packet of a data stream into multiple segments prior to communication of the packet, allowing a packet to be transmitted in smaller chunks. The source processor can process the segments for two or more packets for a given data stream concurrently, and provide appropriate context information in each segments header to facilitate in order transmission and reception of the packets represented by the individual segments. Similarly, a destination processor can receive the packet segments packets for an ordered data stream from a source processor, and can assign different contexts, based upon the context information in each segments header. When a last segment is received for a particular packet, the context for the particular packet is closed, and a descriptor for the packet is sent to a queue. The order in which the last segments of the packets are transmitted maintains order amongst the packets.

Abstract translation: 源处理器可以在分组通信之前将数据流的每个分组划分成多个分段，从而允许以更小的分组发送分组。 源处理器可以对于给定数据流并发地处理两个或更多个分组的分段，并且在每个分段报头中提供适当的上下文信息，以有助于顺序发送和接收由各个分段表示的分组。 类似地，目的地处理器可以从源处理器接收用于有序数据流的分组分段分组，并且可以基于每个分段报头中的上下文信息来分配不同的上下文。 当针对特定分组接收到最后一个分段时，特定分组的上下文被关闭，并且分组的描述符被发送到队列。 传送数据包的最后一个段的顺序维护数据包之间的顺序。

公开(公告)号：US20130282933A1

公开(公告)日：2013-10-24

申请号：US13454505

申请日：2012-04-24

Applicant: Tommi M. Jokinen ,  David B. Kramer ,  Kun Xu

Inventor： Tommi M. Jokinen ,  David B. Kramer ,  Kun Xu

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A DMA controller allocates space at a buffer to different DMA engines based on the length of time data segments have been stored at a buffer. This allocation ensures that DMA engines associated with a destination that is experiencing higher congestion will be assigned less buffer space than a destination that is experiencing lower congestion. Further, the DMA controller is able to adapt to changing congestion conditions at the transfer destinations.

Abstract translation: DMA控制器根据数据段已经存储在缓冲区的时间长度，将缓冲区的空间分配给不同的DMA引擎。 该分配确保与经历较高拥塞的目的地相关联的DMA引擎将被分配比经历较低拥塞的目的地更少的缓冲区空间。 此外，DMA控制器能够适应转移目的地处的变化的拥塞状况。

公开(公告)号：US08560796B2

公开(公告)日：2013-10-15

申请号：US12748617

申请日：2010-03-29

Applicant: Kun Xu ,  David B Kramer

Inventor： Kun Xu ,  David B Kramer

IPC: G06F13/18

CPC classification number: G06F13/1689 ,  G06F12/0215

Abstract: A data processing system employs an improved arbitration process in selecting pending memory access requests received from the one or more processor cores for servicing by the memory. The arbitration process uses memory timing and state information pertaining both to memory access requests already submitted to the memory for servicing and to the pending memory access requests which have not yet been selected for servicing by the memory. The memory timing and state information may be predicted memory timing and state information; that is, the component of the data processing system that implements the improved scheduling algorithm may not be able to determine the exact point in time at which a memory controller initiates a memory access for a corresponding memory access request and thus the component maintains information that estimates or otherwise predicts the particular state of the memory at any given time.

Abstract translation: 数据处理系统采用改进的仲裁过程来选择从一个或多个处理器核心接收到的待存储器访问请求，以便由存储器进行服务。 仲裁过程使用与已经提交到存储器进行服务的存储器访问请求有关的存储器定时和状态信息以及尚未被存储器维护的未决存储器访问请求。 存储器定时和状态信息可以是预测的存储器定时和状态信息; 也就是说，实现改进的调度算法的数据处理系统的组件可能不能够确定存储器控制器针对相应的存储器访问请求启动存储器访问的确切时间点，因此该组件保持估计的信息 或以其他方式预测在任何给定时间的存储器的特定状态。

公开(公告)号：US07861291B2

公开(公告)日：2010-12-28

申请号：US11422063

申请日：2006-06-02

Applicant: David B. Kramer ,  Chris P. Thron ,  Bernard Karl Gunther

Inventor： David B. Kramer ,  Chris P. Thron ,  Bernard Karl Gunther

IPC: G06F17/00

CPC classification number: H04L63/0263 ,  H04L63/101

Abstract: A method, data processing system, and computer program product are provided for retrieving access rules using a plurality of subtables. An incoming packet that includes fields of data is received from a network. A key is formed from the fields, the key includes a number of subkeys. The subkeys are selected and each of the selected subkeys is used to search a different subtable. If a subtable entry is a pointer, a next level subtable is searched until a failure or data is encountered. If a failure occurs, a default rule is applied. If data is encountered, the key is masked using a stored mask value. The resulting masked key is compared to a stored rule. If they match, the identified rule is applied, otherwise the default rule is applied.

Abstract translation: 提供了一种方法，数据处理系统和计算机程序产品，用于使用多个子表检索访问规则。 从网络接收包括数据字段的传入分组。 密钥由字段形成，密钥包括多个子密钥。 选择子项，并且使用每个所选择的子项来搜索不同的子表。 如果子表项是指针，则搜索下一级子表，直到出现故障或数据遇到。 如果发生故障，则应用默认规则。 如果遇到数据，密钥将使用存储的掩码值进行掩码。 将结果掩码的密钥与存储的规则进行比较。 如果匹配，则应用已识别的规则，否则应用默认规则。

公开(公告)号：US07245624B2

公开(公告)日：2007-07-17

申请号：US10085222

申请日：2002-02-28

Applicant: David B. Kramer ,  David P. Sonnier

Inventor： David B. Kramer ,  David P. Sonnier

IPC: H04L12/56

CPC classification number: H04L47/28 ,  H04L47/22 ,  H04L47/50 ,  H04L2012/5675

Abstract: A processor includes scheduling circuitry and an associated interval computation element. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, and is configured for utilization of at least one time slot table in scheduling the data blocks for transmission. The interval computation element, which may be implemented as a script processor, is operative to determine an interval for transmission of one or more data blocks associated with corresponding locations in the time slot table. The transmission interval is adjustable under control of the interval computation element so as to facilitate the maintenance of a desired service level for one or more of the transmission elements. The interval computation element operates under software control in at least one of determining and adjusting the transmission interval, and may be operative to determine periodically if the transmission interval requires adjustment in order to maintain the desired service level for one or more of the transmission elements.

Abstract translation: 处理器包括调度电路和相关的间隔计算元件。 调度电路调度用于从多个传输元件传输的数据块，并且被配置为在调度数据块以便传输时利用至少一个时隙表。 可以实现为脚本处理器的间隔计算元件可用于确定与时隙表中的相应位置相关联的一个或多个数据块的传输间隔。 传输间隔在间隔计算单元的控制下是可调节的，以便于维持一个或多个传输元件的期望的服务水平。 间隔计算单元在软件控制下以确定和调整传输间隔中的至少一个进行操作，并且可以有效地周期性地确定传输间隔是否需要调整，以维持一个或多个传输元件的期望的服务水平。

公开(公告)号：US07215675B2

公开(公告)日：2007-05-08

申请号：US10085771

申请日：2002-02-28

Applicant: David B. Kramer ,  David P. Sonnier

Inventor： David B. Kramer ,  David P. Sonnier

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04L47/6215 ,  H04L47/24 ,  H04L47/50 ,  H04L2012/5675

Abstract: A processor includes scheduling circuitry and a priority computation element associated with the scheduling circuitry. The scheduling circuitry schedules data blocks for transmission from a plurality of transmission elements, in accordance with a transmission priority established by the priority computation element. The priority computation element, which may be implemented as a script processor, is operative to determine a transmission priority for one or more constituent transmission elements in a specified group of such transmission elements. The group of transmission elements corresponds to a first level of an n-level hierarchy of transmission elements, with the constituent transmission elements corresponding to at least one lower level of the n-level hierarchy of transmission elements. The transmission priority is preferably made adjustable under software control so as to facilitate the maintenance of a desired service level for one or more of the transmission elements.

Abstract translation: 处理器包括调度电路和与调度电路相关联的优先级计算单元。 调度电路根据由优先级计算元件建立的传输优先级来调度用于从多个传输单元传输的数据块。 可以被实现为脚本处理器的优先级计算元件可用于确定特定组的这种传输元件中的一个或多个组成传输元件的传输优先级。 传输元件组对应于传输元件的n级层级的第一级，其中组成传输元件对应于传输元件的n级层级的至少一个较低级别。 传输优先级优选地在软件控制下可调节，以便于维护一个或多个传输元件的期望的服务水平。

公开(公告)号：US09733981B2

公开(公告)日：2017-08-15

申请号：US14300762

申请日：2014-06-10

Applicant: Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

Inventor： Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

IPC: G06F9/48 ,  G06F9/46

CPC classification number: G06F9/4881 ,  G06F2209/484

Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

公开(公告)号：US20150355938A1

公开(公告)日：2015-12-10

申请号：US14300762

申请日：2014-06-10

Applicant: Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

Inventor： Tommi M. Jokinen ,  Michael Kardonik ,  David B. Kramer ,  Peter W. Newton ,  John F. Pillar ,  Kun Xu

IPC: G06F9/48

CPC classification number: G06F9/4881 ,  G06F2209/484

Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

Abstract translation: 数据处理系统包括处理器核心和硬件模块。 处理器内核在数据包上执行任务。 订购范围管理器将第一个值存储在第一个存储位置。 第一个值表示启用第一个排序范围中的第一个任务的独占执行。 响应于接收到的放弃指示符，订购范围管理器将第二值存储在第一存储位置中。 第二个值表示第一个排序范围中的第一个任务的排他性执行被禁用。