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公开(公告)号：US11777424B2
公开(公告)日：2023-10-03
申请号：US17494855
申请日：2021-10-06
Inventor： Shih-Chieh Wang , Yong-Yi Jhuang , Ming-Fu Tsai
CPC classification number: H02P6/186 , H02P2207/05
Abstract: A method for determining an initial rotor position of a permanent magnet synchronous motor (PMSM) includes: generating a plurality of transient currents by applying a plurality of voltages to each phase stator winding of a three phase stator winding of the PMSM; generating three phase current differences according to the plurality of transient currents; determining a first zone in which the initial rotor position of the PMSM is located according to the three phase current differences, wherein angles between 0-360 degrees are divided into a plurality of zones, and the first zone is selected from the plurality of zones; calculating three line current differences according to the three phase current differences; and determining the initial rotor position of the PMSM according to the first zone and the three line current differences.
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公开(公告)号：US11727968B2
公开(公告)日：2023-08-15
申请号：US17499870
申请日：2021-10-13
Inventor： Po-Hsun Wu , Jen-Shou Hsu
IPC: G11C7/22
CPC classification number: G11C7/222 , G11C7/225 , G11C2207/2254
Abstract: A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.
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公开(公告)号：US20230237985A1
公开(公告)日：2023-07-27
申请号：US17583235
申请日：2022-01-25
Inventor： HSIN-YUAN CHIU , HSIANG-YU YANG , YA-MIEN HSU
IPC: G10K11/178 , H03G3/00
CPC classification number: G10K11/17813 , H03G3/001
Abstract: An apparatus for noise reduction in audio signal processing includes a power amplifier, a zero-crossing detector, and a threshold detector. The power amplifier has an input signal terminal for receiving an audio input signal and an output signal terminal. The audio input signal is a digital-to-analog converted version according to a version of a digital audio signal. The power amplifier has an analog gain which is controllable in response to an analog gain control signal. The zero-crossing detector determines a zero-crossing detection signal according to an internal signal provided between the input signal terminal and the output signal terminal. The threshold detector determines a gain setting according to the digital audio signal and the zero-crossing detection signal to generate the analog gain control signal indicating the gain setting, wherein the threshold detector controls the analog gain of the power amplifier according to the analog gain control signal.
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公开(公告)号：US20230208180A1
公开(公告)日：2023-06-29
申请号：US17561685
申请日：2021-12-23
Inventor： Yao-Wei Yang
IPC: H02J7/00
CPC classification number: H02J7/007192 , H02J7/007182 , H02J7/00714
Abstract: A linear charger includes a constant current charging circuit and a thermal regulation circuit. The constant current charging circuit is arranged to generate a charging current, and includes a first transconductance amplifier, wherein the first transconductance amplifier has a positive terminal, a negative terminal, and an output terminal. The thermal regulation circuit is coupled to the output terminal and the negative terminal of the first transconductance amplifier, and is arranged to generate and modulate a thermal regulation current and an amplifier reference voltage with temperature, and transmit the thermal regulation current and the amplifier reference voltage to the output terminal and the negative terminal of the first transconductance amplifier, respectively.
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公开(公告)号：US11632088B2
公开(公告)日：2023-04-18
申请号：US17102455
申请日：2020-11-24
Inventor： Yang-Jing Huang , Deng-Yao Shih , Ya-Mien Hsu
Abstract: A voltage converter comprising: a bootstrap circuit, comprising an output capacitor, an error amplifier, a charging control circuit and a charging circuit. The charging control circuit comprises: a detection circuit, configured to detect an output voltage of the output capacitor to generate a detection signal; and a power limiting circuit, configured to clamp an output voltage of the error amplifier to a specific range based on the detection signal. The charging circuit is configured to generate a charging signal according the output voltage of the error amplifier to the bootstrap circuit, to charge the output capacitor.
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Patent Agency Ranking
公开(公告)号：US20230116769A1
公开(公告)日：2023-04-13
申请号：US17499870
申请日：2021-10-13
Inventor： Po-Hsun Wu , Jen-Shou Hsu
IPC: G11C7/22
Abstract: A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.
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27.发明申请公开(公告)号：US20220400341A1
公开(公告)日：2022-12-15
申请号：US17344907
申请日：2021-06-10
Inventor： Hsin-Yuan Chiu , Tsung-Fu Lin
Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.
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公开(公告)号：US11368130B1
公开(公告)日：2022-06-21
申请号：US17179375
申请日：2021-02-18
Inventor： Hsin-Yuan Chiu , Hsiang-Yu Yang
Abstract: A direct current (DC) offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is arranged to detect whether a DC component exists in pulse-width-modulation (PWM) signals and accordingly generate a DC offset detection result. The control circuit is arranged to control an audio system according to the DC offset detection result. The DC offset detection circuit comprises a PWM polarity judgment circuit, a cascaded integrator-comb (CIC) filter and a DC offset judgment circuit. The PWM polarity judgment circuit is arranged to judge a polarity of complementary PWM signals and accordingly generate a polarity indication value. The CIC filter is arranged to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is arranged to generate the DC offset detection result by comparing the filter output signal with a predetermined DC threshold.
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29.发明授权公开(公告)号：US11342030B1
公开(公告)日：2022-05-24
申请号：US17145415
申请日：2021-01-11
Inventor： Ming-Xun Wang
Abstract: An erase voltage compensation mechanism for group erase mode with bit line leakage detection comprises performing a block erase operation by applying an erase voltage. Continue block erasing until bit line leakage is detected upon which the erase voltage is latched and over-erase correction is performed. A compensation voltage value is calculated by finding the difference between an upper bound of a threshold voltage distribution and an erase verify point when the bit line leakage was detected. The latched erase voltage is increased by the compensation voltage to create a compensated voltage. A group erase operation is performed and the group address is incremented by 1 and the compensated voltage value is loaded. Then the group erase operation is performed on the next group. The address is incremented, the compensated voltage is loaded, and the group erase operation is performed until the group is the last group.
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公开(公告)号：US20220149731A1
公开(公告)日：2022-05-12
申请号：US17092310
申请日：2020-11-08
Inventor： Che-Wei Hsu
IPC: H02M3/158 , H03K5/24 , G01R19/165 , H02M1/08
Abstract: A COT (constant on-time) buck converter includes a first transistor, a second transistor, a driver circuit, an inductor, a first resistor, a second resistor, a capacitor, a load, and a feedback loop circuit. The feedback loop circuit includes a first switch, a second switch, an error amplifier, a comparator, a frequency locked loop circuit, an inverter and a COT logic circuit. The COT buck converter is able to improve DC (direct-current) regulation efficiency and transient response time.
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