公开(公告)号：US12094553B2

公开(公告)日：2024-09-17

申请号：US17556363

申请日：2021-12-20

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: G11C7/22 ,  G01R23/02 ,  G06F13/16 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50 ,  H03L1/02 ,  G01R23/15 ,  G01R35/00 ,  G06F1/08 ,  G06F1/12 ,  G06F11/16 ,  G11C7/04

CPC classification number: G11C29/50012 ,  G01R23/02 ,  G06F13/1689 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  H03L1/02 ,  G01R23/15 ,  G01R35/005 ,  G06F1/08 ,  G06F1/12 ,  G06F11/1604 ,  G11C7/04 ,  G11C2207/2254

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

公开(公告)号：US20240119982A1

公开(公告)日：2024-04-11

申请号：US18176121

申请日：2023-02-28

Applicant: DELL PRODUCTS L.P.

Inventor： Isaac Q. Wang ,  Lee B. Zaretsky

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/173

CPC classification number: G11C7/225 ,  G11C7/109 ,  H03K19/1737

Abstract: A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.

公开(公告)号：US20240111695A1

公开(公告)日：2024-04-04

申请号：US18538263

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su JEONG ,  Hangi Jung ,  Wangsoo Kim ,  Hae Young Chung

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18

CPC classification number: G06F13/1673 ,  G06F13/4086 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C2207/2254

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US11888489B2

公开(公告)日：2024-01-30

申请号：US17888199

申请日：2022-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junsub Yoon ,  Hun-Dae Choi

IPC: H03L7/081 ,  G11C7/22 ,  H03L7/083

CPC classification number: H03L7/0818 ,  G11C7/222 ,  G11C7/225 ,  H03L7/083 ,  H03L7/0814 ,  H03L7/0816

Abstract: In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.

公开(公告)号：US11887652B2

公开(公告)日：2024-01-30

申请号：US17404246

申请日：2021-08-17

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Lei Zhu

IPC: G11C5/14 ,  G11C11/4076 ,  G11C7/22 ,  G11C7/04 ,  G11C11/4074

CPC classification number: G11C11/4076 ,  G11C7/04 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4074

Abstract: Provided are a control circuit and a delay circuit. The control circuit includes a control unit, a first feedback unit, and a second feedback unit. The first feedback unit outputs a first feedback signal according to a voltage of the control unit and a first reference voltage. The second feedback unit outputs a second feedback signal according to a voltage output by the first feedback unit and a second reference voltage. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the first feedback signal and adjust a voltage of a third terminal of the control unit according to the second feedback signal, to make a change value, changing along with a first parameter, of a current of the control unit be within a first range.

公开(公告)号：US20240029770A1

公开(公告)日：2024-01-25

申请号：US18310302

申请日：2023-05-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/156 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C11/4076 ,  H03K5/1565 ,  G11C7/1063 ,  G11C7/225 ,  G11C7/109

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US20230402073A1

公开(公告)日：2023-12-14

申请号：US17968374

申请日：2022-10-18

Applicant: SK hynix Inc.

Inventor： Sang Geun BAE ,  Seung Jin PARK

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C2207/2281 ,  G11C2207/2254 ,  G11C7/225

Abstract: A semiconductor system includes a first semiconductor device configured to output a clock and pattern data, configured to receive a strobe signal and output data, and configured to adjust a duty ratio of the strobe signal by comparing odd data and even data that are generated from the output data and the pattern data, in synchronization with the strobe signal and a second semiconductor device configured to store the pattern data in synchronization with the clock, configured to output the clock as the strobe signal by adjusting a duty ratio of the clock, and configured to output the stored pattern data as the output data.

公开(公告)号：US20230368824A1

公开(公告)日：2023-11-16

申请号：US18052976

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Lee ,  Daehyun Kwon ,  Jang-Woo Ryu ,  Hangi Jung

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/225

Abstract: An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.

公开(公告)号：US11742009B2

公开(公告)日：2023-08-29

申请号：US17688420

申请日：2022-03-07

Applicant: SK hynix Inc.

Inventor： Hyun Seung Kim

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C7/225 ,  G11C2207/2272

Abstract: A semiconductor device includes a pre-pulse generation circuit configured to generate a pre-pulse, based on a write shifting pulse and a write leveling activation signal; a write control signal generation circuit configured to generate a write control signal, based on the pre-pulse and a division clock; and a write leveling control circuit configured to generate detection data including information on a phase difference between a data clock and a system clock, based on the pre-pulse and the division clock.

公开(公告)号：US20190244644A1

公开(公告)日：2019-08-08

申请号：US15890943

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Yoshiya Komatsu ,  Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C8/10

CPC classification number: G11C7/222 ,  G11C7/225 ,  G11C8/10 ,  H03L7/08

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.