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公开(公告)号：US09793867B2
公开(公告)日：2017-10-17
申请号：US15331857
申请日：2016-10-22
Applicant: ESS Technology, Inc.
Inventor： Peter John Frith , Yongsheng Xu , A. Martin Mallinson , Robert Lynn Blair
CPC classification number: H03F3/2173 , H03F1/0227 , H03F3/185 , H03F2200/03 , H04R3/04
Abstract: An apparatus and method are disclosed for providing output signal swings that are greater than the supply voltage in a class-D amplifier. The amplifier circuit boosts the voltage across the amplifier load, such as a loudspeaker, by using capacitors to “charge pump” the voltage across the load and thus increase the voltage temporarily. This is done by using two or more output bridges rather than one, and connecting the bridges through the capacitors. For signals of less than the supply voltage, only an inner bridge, similar to a full bridge of the prior art, operates. For signals above the supply voltage, an outer bridge charges capacitors, which are then used to ‘boost’ the voltage on the bridge output for the short period of the Class-D switching period. Thus, only relatively small value boosting capacitors are needed, as they do not need to supply charge for very long.
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公开(公告)号：US20170126187A1
公开(公告)日：2017-05-04
申请号：US15261938
申请日：2016-09-10
Applicant: ESS Technology, Inc.
Inventor： Peter John Frith , Yongsheng Xu , A. Martin Mallinson , Robert Lynn Blair
CPC classification number: H03F3/2173 , H03F1/0205 , H03F1/0233 , H03F1/3205 , H03F3/185 , H03F3/217 , H03F3/2171 , H03F3/2175 , H03F3/3061 , H03F3/68 , H03F2200/03 , H04R3/00 , H04R3/04
Abstract: An apparatus and method are disclosed for providing output signal swings that are greater than the supply voltage in a class-D amplifier. The amplifier circuit boosts the voltage across the amplifier load, such as a loudspeaker, by using capacitors to “charge pump” the voltage across the load and thus increase the voltage temporarily. This is done by using two or more output bridges rather than one, and connecting the bridges through the capacitors. For signals of less than the supply voltage, only an inner bridge, similar to a full bridge of the prior art, operates. For signals above the supply voltage, an outer bridge charges capacitors, which are then used to ‘boost’ the voltage on the bridge output for the short period of the Class-D switching period. Thus, only relatively small value boosting capacitors are needed, as they do not need to supply charge for very long.
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23.发明申请公开(公告)号：US20170111743A1
公开(公告)日：2017-04-20
申请号：US15261937
申请日：2016-09-10
Applicant: ESS Technology, Inc.
Inventor： Peter John Frith , Frederic Schrive , Hwang Soo Son , Dustin Dale Forman
CPC classification number: H04R5/04 , H04R29/001 , H04R2420/01 , H04R2420/05 , H04R2499/11
Abstract: An apparatus and method is disclosed for achieving improved sound quality from mobile ‘hifi’ playback devices by driving compatible headphones in ‘balanced’ or ‘differential’ mode via standard size headphone connectors on the device, while retaining full compliance with legacy jack connections and conventional headphones. When a headphone is connected, a smartphone may determine whether the headphone is one capable of accepting balanced audio signals, or one that uses a conventional 3-pole jack or a 4-pole CTIA or OMTP jack. For a headphone that accepts balanced audio signals, the four poles of a 4-pole jack are used to drive left and right audio channels, and inverted left and right audio channels. For conventional 3-pole or 4-pole jacks, switches in the smartphone adapt the audio output signals to the configuration expected by the headphone.
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公开(公告)号：US09490774B2
公开(公告)日：2016-11-08
申请号：US14619940
申请日：2015-02-11
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson
Abstract: Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital-to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.
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25.发明申请Finite Impulse Response Filter For Producing Outputs Having Different Phases 审中-公开用于生产不同阶段的输出的有限脉冲响应滤波器公开(公告)号：US20160154914A1
公开(公告)日：2016-06-02
申请号：US15019445
申请日：2016-02-09
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson , Hu Jing Yao , Dustin Forman
IPC: G06F17/50 , H03K5/1536 , H03K5/15
CPC classification number: G06F17/5009 , H03H15/02 , H03K5/15 , H03K5/1536
Abstract: A method and system for designing and implementing a finite impulse response (FIR) filter to create a plurality of output signals, each output signal having the same frequency but at a different phase shift from the other output(s), is described. Values are determined for the resistors, or other elements having impedance values, in a FIR filter having a plurality of outputs, such that each output has the same frequency response but a different phase than the other output(s). This is accomplished by the inclusion of a phase factor in the time domain calculation of the resistor values that does not change the response in the frequency domain. The phase shift is constant and independent of the frequency of the output signal.
Abstract translation: 描述了一种用于设计和实现有限脉冲响应（FIR）滤波器以产生多个输出信号的方法和系统，每个输出信号具有相同的频率但与另一个输出具有不同的相移。 在具有多个输出的FIR滤波器中，确定具有阻抗值的电阻器或其他元件的值，使得每个输出具有与其它输出相同的频率响应但不同的相位。 这是通过在不改变频域响应的电阻值的时域计算中包括相位因子来实现的。 相移是恒定的，与输出信号的频率无关。
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Patent Agency Ranking
公开(公告)号：US09323959B2
公开(公告)日：2016-04-26
申请号：US13848272
申请日：2013-03-21
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson
CPC classification number: G06G7/02 , G06G7/625 , H03H15/023
Abstract: A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements, devices providing for adjustable impedances, or buffers is described. An input signal is sampled in a round robin fashion by a plurality of switches and capacitors. The capacitors are connected directly to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter, adjusted to compensate for the decay of samples in the capacitors between samples. The impedance devices in each set are connected to the capacitors in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the capacitor contains a new sample of the input signal. Switches connect the sets of impedance devices to an output and a virtual ground, only one switch being connected to the output at a time to provide the output signal.
Abstract translation: 描述了提供具有同时存在的所有必要系数组的旋转系数FIR滤波器的电路，而不需要延迟元件，提供可调节阻抗的装置或缓冲器。 通过多个开关和电容器以循环方式对输入信号进行采样。 电容器直接连接到一组阻抗器件上。 每组阻抗器件实现滤波器所需频率响应的系数，被调整以补偿样本之间的电容器中样本的衰减。 每组中的阻抗器件以彼此不同的顺序连接到电容器，使得当电容器中的不同电容器包含输入信号的新采样时，每组阻抗器件将产生所需的频率响应。 开关将阻抗器件组连接到输出和虚拟接地，一次只有一个开关连接到输出端以提供输出信号。
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公开(公告)号：US20160079943A1
公开(公告)日：2016-03-17
申请号：US14569079
申请日：2014-12-12
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson
CPC classification number: H03F3/45076 , H03F1/0205 , H03F1/34 , H03F3/45475 , H03F3/45941 , H03F3/4595 , H03F2200/09 , H03F2203/45114 , H03F2203/45116 , H03F2203/45138 , H03F2203/45224 , H03F2203/45336 , H03F2203/45416 , H03F2203/45446 , H03F2203/45521 , H03F2203/45528 , H03F2203/45594
Abstract: An apparatus is disclosed for providing a common mode voltage to the inputs of a first differential amplifier which outputs the difference between two signals. A second differential amplifier receives the output of the first differential amplifier, and the output of the second differential amplifier is fed back to the inputs of the first differential amplifier as a common mode voltage. Since both inputs of the first differential amplifier receive the fed hack common mode voltage, the first differential amplifier still outputs only the difference in the two signals, but the presence of the common mode voltage allows the first differential amplifier to operate with lower noise if the voltage levels of the inputs to the first differential amplifier vary. The second differential amplifier may be of significantly lower quality and cost than the first differential amplifier, without affecting the performance of the first differential amplifier.
Abstract translation: 公开了一种用于向输出两个信号之间的差的第一差分放大器的输入端提供共模电压的装置。 第二差分放大器接收第一差分放大器的输出，第二差分放大器的输出作为共模电压被反馈到第一差分放大器的输入端。 由于第一差分放大器的两个输入都接收馈电的黑客共模电压，所以第一差分放大器仍然仅输出两个信号的差值，但是共模电压的存在允许第一差分放大器以较低的噪声运行，如果 第一差分放大器的输入的电压电平变化。 第二差分放大器的质量和成本可能比第一差分放大器低得多，而不影响第一差分放大器的性能。
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公开(公告)号：US09264019B2
公开(公告)日：2016-02-16
申请号：US14321390
申请日：2014-07-01
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson
CPC classification number: H03H17/06 , H03H17/0229 , H03H17/0248 , H03H17/0286 , H03H17/0294 , H03H21/0012 , H03H21/002
Abstract: FIR filters for compensating for fixed pattern jitter, and methods of constructing the same, are disclosed. In one embodiment, a FIR filter filters a signal having a desired frequency component, with the coefficients of the FIR filter selected so that the filter is the equivalent of two combined FIR filters, one having the desired frequency at the filter's peak output frequency, and a second in which the signal is delayed by a time equal to half of a period of a different frequency which is desired to be removed from the output signal. In another embodiment, a FIR filter includes a delay line with a total delay longer than the period of the jitter. A signal is passed down the delay line, the number of signal edges that have occurred as the signal passes each delay element in the counted. Drivers corresponding to the delay elements in which a number of signal edges occur at the desired frequency during the period of fixed pattern jitter activate impedance elements attached to those delay elements. A processor configures the activated impedance elements to provide the desired filter response.
Abstract translation: 公开了用于补偿固定模式抖动的FIR滤波器及其构造方法。 在一个实施例中，FIR滤波器对具有期望频率分量的信号进行滤波，其中选择FIR滤波器的系数，使得滤波器等效于两个组合的FIR滤波器，一个具有滤波器峰值输出频率处的期望频率， 第二个信号被延迟等于期望从输出信号去除的不同频率的周期的一半的时间。 在另一个实施例中，FIR滤波器包括具有比抖动周期长的总延迟的延迟线。 信号沿着延迟线传递，当信号通过计数的每个延迟元件时，发生的信号边沿的数量。 对应于在固定图案抖动的周期期间以期望频率出现的信号边缘数量的延迟元件的驱动器激活附接到这些延迟元件的阻抗元件。 处理器配置激活的阻抗元件以提供期望的滤波器响应。
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公开(公告)号：US09130645B2
公开(公告)日：2015-09-08
申请号：US14022155
申请日：2013-09-09
Applicant: ESS Technology, Inc.
Inventor： Robert Lynn Blair , A. Martin Mallinson
CPC classification number: H04B1/26 , H04B1/0007
Abstract: A method and system is disclosed for simultaneously down-converting multiple selected signals, such as RF signals, into adjacent ranges in an intermediate frequency band so that the total resulting bandwidth, and thus the sampling rate required to digitize the signal, is minimized. A first signal is down-converted into a range starting at a lowest selected frequency in the IF band. The next signal is down-converted, into a range higher than, but near or adjacent to, the down-converted range of the first signal, and so on. A guard band may be left between the signals if desired. In this way, the selected signals occupy the minimum bandwidth required. When the selection of signals to be down-converted is changed, the frequency ranges are dynamically adjusted so that the signals being down-converted always occupy the lowest ranges of the IF band.
Abstract translation: 公开了一种方法和系统，用于同时将多个所选信号（例如RF信号）下变频到中间频带中的相邻范围，使得总结果带宽以及因此将信号数字化所需的采样率最小化。 第一信号被下变频到从IF频段中最低选定频率开始的范围。 下一个信号被降频转换成高于第一信号的下变频范围但接近或相邻的范围，等等。 如果需要，保护带可能会留在信号之间。 以这种方式，所选择的信号占用所需的最小带宽。 当要降低转换的信号的选择被改变时，动态地调节频率范围，使得被降频转换的信号总是占据IF频带的最低范围。
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公开(公告)号：US08937506B2
公开(公告)日：2015-01-20
申请号：US13848216
申请日：2013-03-21
Applicant: ESS Technology, Inc.
Inventor： A. Martin Mallinson
CPC classification number: H03H7/0138 , H03H15/00
Abstract: A circuit that provides a rotating coefficient FIR filter with all necessary coefficient sets present at the same time, without the need for delay elements or devices providing for adjustable impedances is described. An input signal is sampled in round robin fashion by a plurality of sample and hold devices. The outputs of the sample and hold devices are connected to sets of impedance devices. Each set of impedance devices implements the coefficients of the desired frequency response of the filter. The impedance devices in each set are connected to the sample and hold devices in a different order from each other set, so that each set of impedance devices will produce the desired frequency response when a different one of the sampling circuits contains a new sample of the input signal. Switches connect the sets of impedance devices to an output, only one switch being closed at a time to provide the output signal.
Abstract translation: 描述了提供具有同时存在的所有必要系数组的旋转系数FIR滤波器的电路，而不需要提供可调阻抗的延迟元件或器件。 通过多个采样和保持装置以循环方式对输入信号进行采样。 采样和保持设备的输出连接到一组阻抗设备。 每组阻抗器件实现滤波器所需频率响应的系数。 每组中的阻抗装置以彼此不同的顺序连接到采样和保持装置，使得当不同的采样电路包含新的采样电路时，每组阻抗装置将产生期望的频率响应 输入信号。 开关将阻抗器件组连接到输出端，一次只有一个开关闭合以提供输出信号。
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