System and method for optimized preemption and reservation of software locks
    21.
    发明申请
    System and method for optimized preemption and reservation of software locks 审中-公开
    用于优化软件锁抢占和预约的系统和方法

    公开(公告)号:US20070136725A1

    公开(公告)日:2007-06-14

    申请号:US11301104

    申请日:2005-12-12

    IPC分类号: G06F9/46

    CPC分类号: G06F9/526 G06F2209/522

    摘要: A system and method is provided that reserves a software lock for a waiting thread is presented. When a software lock is released by a first thread, a second thread that is waiting for the same resource controlled by the software lock is woken up. In addition, a reservation to the software lock is established for the second thread. After the reservation is established, if the lock is available and requested by a thread other than the second thread, the requesting thread is denied, added to the wait queue, and put to sleep. In addition, the reservation is cleared. After the reservation has been cleared, the lock will be granted to the next thread to request the lock.

    摘要翻译: 提供了一种保留用于等待线程的软件锁的系统和方法。 当软件锁由第一个线程释放时,等待软件锁定的相同资源的第二个线程被唤醒。 另外,针对第二线程建立对软件锁定的预约。 在建立预留之后,如果第二线程之外的线程可用并请求该锁,则请求线程被拒绝,被添加到等待队列中并进入休眠状态。 此外,预订已被清除。 预订清除后,锁将被授予下一个线程以请求锁定。

    System and method for implementing a fast file synchronization in a data processing system
    22.
    发明申请
    System and method for implementing a fast file synchronization in a data processing system 失效
    用于在数据处理系统中实现快速文件同步的系统和方法

    公开(公告)号:US20070101052A1

    公开(公告)日:2007-05-03

    申请号:US11259898

    申请日:2005-10-27

    IPC分类号: G06F12/00

    摘要: A system and method for implementing a fast file synchronization in a data processing system. A memory management unit divides a file stored in system memory into a collection of data block groups. In response to a master (e.g., processing unit, peripheral, etc.) modifying a first data block group among the collection of data block groups, the memory management unit writes a first block group number associated with the first data block group to system memory. In response to a master modifying a second data block group, the memory management unit writes the first data block group to a hard disk drive and writes a second data block group number associated with the second data block group to system memory. In response to a request to update modified data block groups of the file stored in the system memory to the hard disk drive, the memory management unit writes the second data block to the hard disk drive.

    摘要翻译: 一种用于在数据处理系统中实现快速文件同步的系统和方法。 存储器管理单元将存储在系统存储器中的文件划分成数据块组的集合。 响应于在数据块组的集合中修改第一数据块组的主(例如,处理单元,外围设备等),存储器管理单元将与第一数据块组相关联的第一块组号写入系统存储器 。 响应于主修改第二数据块组,存储器管理单元将第一数据块组写入硬盘驱动器,并将与第二数据块组相关联的第二数据块组编号写入系统存储器。 响应于将存储在系统存储器中的文件的修改的数据块组更新到硬盘驱动器的请求,存储器管理单元将第二数据块写入硬盘驱动器。

    Method and apparatus for aging data in a cache
    23.
    发明申请
    Method and apparatus for aging data in a cache 有权
    用于在缓存中老化数据的方法和装置

    公开(公告)号:US20070038809A1

    公开(公告)日:2007-02-15

    申请号:US11201642

    申请日:2005-08-11

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0897 G06F12/0891

    摘要: A computer implemented method, apparatus, and computer usable code for managing cache data. A partition identifier is associated with a cache entry in a cache, wherein the partition identifier identifies a last partition accessing the cache entry. The partition identifier associated with the cache entry is compared with a previous partition identifier located in a processor register in response to the cache entry being moved into a lower level cache relative to the cache. The cache entry is marked if the partition identifier associated with the cache entry matches the previous partition identifier located in the processor register to form a marked cache entry, wherein the marked cache entry is aged at a slower rate relative to an unmarked cache entry.

    摘要翻译: 计算机实现的方法,装置和用于管理高速缓存数据的计算机可用代码。 分区标识符与高速缓存中的高速缓存条目相关联,其中分区标识符标识访问高速缓存条目的最后一个分区。 与高速缓存条目相关联的分区标识符与位于处理器寄存器中的先前分区标识符进行比较,以响应于高速缓存条目相对于高速缓存移动到较低级高速缓存。 如果与高速缓存条目相关联的分区标识与位于处理器寄存器中的先前分区标识符相匹配以形成标记的高速缓存条目,则标记高速缓存条目,其中标记的高速缓存条目相对于未标记的高速缓存条目以较慢的速率进行老化。

    Interrupt thresholding for SMT and multi processor systems
    24.
    发明申请
    Interrupt thresholding for SMT and multi processor systems 审中-公开
    SMT和多处理器系统的中断阈值

    公开(公告)号:US20060112208A1

    公开(公告)日:2006-05-25

    申请号:US10996307

    申请日:2004-11-22

    IPC分类号: G06F13/24 G06F13/26

    CPC分类号: G06F13/26

    摘要: A method, system and computer program product for processing interrupts in a multi-processor system is provided. The method, system and computer program product process interrupts utilizing an unequal scheduling policy in order to achieve SLA target goals for interrupt processing. In a method of the present invention an interrupt is received. A determination is made as to whether the interrupt is assigned to a specific processor. If the interrupt is not assigned to a specific processor then a processor is selected from the group of processors based on their respective interrupt priority levels. Specifically, one processor is selected from all the processors that have the highest interrupt priority level. After the interrupt has been processed by the selected processor, a determination is made as to whether the selected processor has exceeded its threshold processing level. If threshold processing level has been exceeded, the selected processor's interrupt priority level is lowered.

    摘要翻译: 提供了一种用于处理多处理器系统中断的方法,系统和计算机程序产品。 方法,系统和计算机程序产品过程中断利用不平等的调度策略,以实现中断处理的SLA目标目标。 在本发明的方法中,接收中断。 确定中断是否被分配给特定的处理器。 如果中断未被分配给特定的处理器,那么根据它们各自的中断优先级来从处理器组中选择一个处理器。 具体来说,从具有最高中断优先级的所有处理器中选择一个处理器。 在所选择的处理器处理了中断之后,确定所选择的处理器是否已超过其阈值处理级别。 如果超过阈值处理级别,则所选处理器的中断优先级降低。

    System and method for dynamically adjusting read ahead values based upon memory usage
    25.
    发明申请
    System and method for dynamically adjusting read ahead values based upon memory usage 失效
    基于内存使用动态调整预读值的系统和方法

    公开(公告)号:US20050235125A1

    公开(公告)日:2005-10-20

    申请号:US10828455

    申请日:2004-04-20

    IPC分类号: G06F12/00 G06F12/02 G06F12/08

    CPC分类号: G06F12/023

    摘要: A system and method for dynamically altering a Virtual Memory Manager (VMM) Sequential-Access Read Ahead settings based upon current system memory conditions is provided. Normal VMM operations are performed using the Sequential-Access Read Ahead values set by the user. When low memory is detected, the system either turns off Sequential-Access Read Ahead operations or decreases the maximum page ahead (maxpgahead) value based upon whether the amount of free space is simply low or has reached a critically low level. The altered VMM Sequential-Access Read Ahead state remains in effect until enough free space is available so that normal VMM Sequential-Access Read Ahead operations can be performed (at which point the altered Sequential-Access Read Ahead values are reset to their original levels).

    摘要翻译: 提供了一种基于当前系统内存条件动态更改虚拟内存管理器(VMM)顺序访问预读设置的系统和方法。 使用用户设置的顺序访问读取前值可以执行正常的VMM操作。 当检测到低内存时,系统会根据自由空间量是否很低或已经达到极低的水平,关闭顺序访问预读操作或者减小最大页面前提(maxpgahead)值。 改变的VMM顺序访问预读状态在有足够的可用空间可用之前保持有效,以便可以执行正常的VMM顺序访问预读操作(此时,改变的顺序访问读取前置值被重置为其原始级别) 。

    Method and data processing system for per-chip thread queuing in a multi-processor system
    26.
    发明申请
    Method and data processing system for per-chip thread queuing in a multi-processor system 审中-公开
    多处理器系统中每芯片线程排队的方法和数据处理系统

    公开(公告)号:US20050210472A1

    公开(公告)日:2005-09-22

    申请号:US10803659

    申请日:2004-03-18

    IPC分类号: G06F9/46 G06F9/50

    CPC分类号: G06F9/505 G06F9/5033

    摘要: A method, computer program product, and a data processing system for queuing threads among a plurality of processors in a multiple processor system having a plurality of multi-processor modules is provided. A first thread to be processed is received and is identified as part of an existing process. A search for an idle processor is performed. The search is restricted to processors of a first multi-processor module associated with the existing process.

    摘要翻译: 提供了一种用于在具有多个多处理器模块的多处理器系统中的多个处理器之间排队线程的方法,计算机程序产品和数据处理系统。 被处理的第一个线程被接收并被识别为现有过程的一部分。 执行空闲处理器的搜索。 该搜索仅限于与现有进程相关联的第一多处理器模块的处理器。

    System and method for delayed priority boost
    27.
    发明申请
    System and method for delayed priority boost 有权
    用于延迟优先级提升的系统和方法

    公开(公告)号:US20050022186A1

    公开(公告)日:2005-01-27

    申请号:US10626192

    申请日:2003-07-24

    IPC分类号: G06F9/46

    CPC分类号: G06F9/52 G06F9/4818

    摘要: A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.

    摘要翻译: 提供了一种用于延迟执行线程的优先级提升的系统和方法。 当线程准备进入代码的关键部分时,例如当线程利用共享系统资源时,更新用户模式可访问数据区域,指示线程处于关键部分,并且如果内核接收到抢占事件, 线程应该接收的优先级提升。 如果内核在线程完成关键部分之前收到抢占事件,则内核将代表线程应用优先级提升。 通常,线程将完成关键部分,而无需实际提升优先级。 如果线程确实接收到实际的优先级提升,那么在关键部分完成之后,内核会将线程的优先级重置为正常级别。