公开(公告)号：US06606732B2

公开(公告)日：2003-08-12

申请号：US09734515

申请日：2000-12-11

申请人： Patrick H. Buffet ,  Craig Lussier ,  Joseph Natonio

发明人： Patrick H. Buffet ,  Craig Lussier ,  Joseph Natonio

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： An automated method of selecting differential pairs in an integrated circuit comprising loading the design database for the integrated circuit package, and selecting output parameters for the differential pairs comprises adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The method then includes comparing the output parameters to the design in the design database, and obtaining a resulting differential pairs list. The differential pair list preferably includes differential signal pairs having electrical characteristics within a predetermined design tolerance range. At least some of the differential signal pairs may comprise individual wires or connectors not physically adjacent one another.

公开(公告)号：US20090004978A1

公开(公告)日：2009-01-01

申请号：US11769128

申请日：2007-06-27

申请人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Joseph Natonio ,  James D. Rockrohr ,  Huihao Xu ,  Steven J. Zier

发明人： Louis L. Hsu ,  Hayden C. Cranford, Jr. ,  Joseph Natonio ,  James D. Rockrohr ,  Huihao Xu ,  Steven J. Zier

IPC分类号： H04B1/04 ,  G08B21/00 ,  H04L27/00 ,  H04B1/02

CPC分类号： H04L25/0286 ,  H04L25/0272

摘要： A method is provided for operating a transmitter integrated in a microelectronic element. In a calibration phase, a plurality of operational parameters are stored for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. Upon detecting an operating condition such as a temperature or power supply voltage level, the corresponding stored operational parameter is applied to the transmitter to control the frequency response.

摘要翻译： 提供了一种用于操作集成在微电子元件中的发射器的方法。 在校准阶段中，存储多个操作参数，用于在多个对应的操作条件中的每一个下控制发射机的频率响应。 在检测到诸如温度或电源电压电平的操作条件时，将相应的存储的操作参数应用于发射机以控制频率响应。

公开(公告)号：US20080180139A1

公开(公告)日：2008-07-31

申请号：US11668137

申请日：2007-01-29

申请人： Joseph Natonio ,  Steven J. Zier

发明人： Joseph Natonio ,  Steven J. Zier

IPC分类号： H03K3/356 ,  H03B19/00

CPC分类号： H03K3/356121 ,  H03K3/35625

摘要： A CMOS rail-to-rail differential latch is provided in which a plurality of cross-coupled devices pull first and second nodes of the latch to opposite rail-to-rail voltages. Desirably, first and second output isolating elements have inputs coupled to the first and second nodes, the output isolating elements being operable to output versions of the opposite rail-to-rail voltages as a true and a complementary output of the latch. In this way, the true output has a rising edge occurring simultaneously with a falling edge of the complementary output. The complementary output has a rising edge occurring simultaneously with a falling edge of the true output. First and second input isolating elements of the latch have outputs coupled to the first and second nodes, the first and second input isolating elements being operable to apply versions of input signals to the first and second nodes.

摘要翻译： 提供了CMOS轨对轨差分锁存器，其中多个交叉耦合器件将锁存器的第一和第二节点拉到相对的轨到轨电压。 期望地，第一和第二输出隔离元件具有耦合到第一和第二节点的输入，输出隔离元件可操作以将相对的轨至轨电压的版本输出为锁存器的真实和互补输出。 以这种方式，真正的输出具有与互补输出的下降沿同时出现的上升沿。 互补输出具有与真实输出的下降沿同时发生的上升沿。 锁存器的第一和第二输入隔离元件具有耦合到第一和第二节点的输出，第一和第二输入隔离元件可操作以将输入信号的版本应用于第一和第二节点。

公开(公告)号：US07397261B2

公开(公告)日：2008-07-08

申请号：US11380515

申请日：2006-04-27

申请人： Louis Lu-Chen Hsu ,  Edward R. Pillai ,  Joseph Natonio ,  James D. Rockrohr ,  David R. Hanson

发明人： Louis Lu-Chen Hsu ,  Edward R. Pillai ,  Joseph Natonio ,  James D. Rockrohr ,  David R. Hanson

IPC分类号： G01R31/26

CPC分类号： G01R31/2884 ,  G01R31/3008 ,  G01R31/318577

摘要： A universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.

摘要翻译： 一种通用泄漏监测系统（ULMS），用于在开发制造过程或正常运行期间测量多个泄漏宏。 ULMS表征了栅极电介质泄漏，亚阈值泄漏和反向偏置结漏电以及n型和p型CMOS器件的泄漏等。 使用片上算法从第一测试宏到最后一个测试宏顺序执行测试。 当测试最后一个测试宏时，会扫描泄漏数据。

公开(公告)号：US07358787B2

公开(公告)日：2008-04-15

申请号：US11307923

申请日：2006-02-28

申请人： Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

发明人： Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

IPC分类号： H03K3/289

CPC分类号： H03K3/356043

摘要： A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.

摘要翻译： 提供了一种双用途电流模式逻辑（“CML”）锁存电路，其包括可操作以接收至少一对差分输入数据信号和至少一个时钟信号的CML锁存器。 CML锁存器可操作以根据输入差分数据信号对的状态产生至少一个输出信号。 模式控制装置可操作以接收模式控制信号以将CML锁存器作为缓冲器或锁存器操作。 以这种方式，当模式控制信号无效时，CML锁存器产生并以由至少一个时钟信号确定的定时锁存输出信号，并且当模式控制信号有效时，CML锁存器产生输出信号，使得 每当差分输入数据信号对的状态改变时，输出信号就会改变。

公开(公告)号：US20070252613A1

公开(公告)日：2007-11-01

申请号：US11380515

申请日：2006-04-27

申请人： Louis Hsu ,  Edward Pillai ,  Joseph Natonio ,  James Rockrohr ,  David Hanson

发明人： Louis Hsu ,  Edward Pillai ,  Joseph Natonio ,  James Rockrohr ,  David Hanson

IPC分类号： G01R31/26

CPC分类号： G01R31/2884 ,  G01R31/3008 ,  G01R31/318577

摘要： The invention provides a universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.

摘要翻译： 本发明提供了一种通用泄漏监测系统（ULMS），用于在开发制造过程或正常操作期期间测量多个泄漏宏。 ULMS表征了栅极电介质泄漏，亚阈值泄漏和反向偏置结漏电以及n型和p型CMOS器件的泄漏等。 使用片上算法从第一测试宏到最后一个测试宏顺序执行测试。 当测试最后一个测试宏时，会扫描泄漏数据。

公开(公告)号：US20070200605A1

公开(公告)日：2007-08-30

申请号：US11307923

申请日：2006-02-28

申请人： Joseph Marsh ,  Joseph Natonio ,  James Wilson

发明人： Joseph Marsh ,  Joseph Natonio ,  James Wilson

IPC分类号： H03K3/356

CPC分类号： H03K3/356043

摘要： A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.

摘要翻译： 提供了一种双用途电流模式逻辑（“CML”）锁存电路，其包括可操作以接收至少一对差分输入数据信号和至少一个时钟信号的CML锁存器。 CML锁存器可操作以根据输入差分数据信号对的状态产生至少一个输出信号。 模式控制装置可操作以接收模式控制信号以将CML锁存器作为缓冲器或锁存器操作。 以这种方式，当模式控制信号无效时，CML锁存器产生并以由至少一个时钟信号确定的定时锁存输出信号，并且当模式控制信号有效时，CML锁存器产生输出信号，使得 每当差分输入数据信号对的状态改变时，输出信号就会改变。

公开(公告)号：US06680681B1

公开(公告)日：2004-01-20

申请号：US10249795

申请日：2003-05-08

申请人： Louis L. Hsu ,  William R. Kelly ,  Joseph Natonio ,  Karl D. Selander ,  Michael A. Sorna

发明人： Louis L. Hsu ,  William R. Kelly ,  Joseph Natonio ,  Karl D. Selander ,  Michael A. Sorna

IPC分类号： H03M110

CPC分类号： H04L25/0288 ,  H03M1/661 ,  H03M1/742

摘要： A transmitter for driving a transmission medium employs pre-distortion to predistort the signals leaving the driver so that they will have an acceptable shape when they reach their destination and have been distorted by imperfections in the transmission medium. The change to pulse height is accomplished by means of a current steering unit that directs a controllable amount of current into the line for each pulse while maintaining the total sum of current that is generated constant in order to reduce noise. Control coefficients for the current steering unit are manipulated in an nxm register that automatically maintains the total number of bits constant while bits are moved from a location that controls a first current driver to a location that controls a second current driver with different properties.

摘要翻译： 用于驱动传输介质的发射机使用预失真来预先离开驾驶员的信号，使得当它们到达其目的地并且由于传输介质中的缺陷而变形时，它们将具有可接受的形状。 脉冲高度的改变是通过一个电流转向单元实现的，该电流转向单元将可控量的电流引导到每个脉冲的线中，同时保持恒定的电流的总和以减少噪声。 用于当前转向单元的控制系数在nxm寄存器中进行操作，该nxm寄存器自动维持总位数恒定，而位从控制第一当前驱动器的位置移动到控制具有不同属性的第二当前驱动器的位置。