公开(公告)号：US07560966B2

公开(公告)日：2009-07-14

申请号：US12002878

申请日：2007-12-19

申请人： Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

发明人： Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

IPC分类号： H03K3/289

CPC分类号： H03K3/356043

摘要： A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at least one clock signal and having a mode control device for operating the CML latch circuit as a buffer amplifier when the at least one clock signal is inactive. The method comprises the steps of activating the mode control devices of each of the CML latches to operate each of the CML latches as a buffer; inputting a first signal to a first CML latch of the series; latching an output signal of a second CML latch of the series, the second CML latch being connected at a point in the series downstream from the first CML latch; and determining whether the output signal changes in accordance with a change in the first signal.

摘要翻译： 提供了通过串联连接的多个双用途电流模式逻辑（“CML”）锁存电路来测试连接性的方法。 每个CML锁存电路可操作以根据至少一个时钟信号在定时锁存至少一个输出信号，并具有一个模式控制装置，用于当至少一个时钟信号为 不活动 该方法包括以下步骤：激活每个CML锁存器的模式控制装置，以操作每个CML锁存器作为缓冲器; 向所述系列的第一CML锁存器输入第一信号; 锁存串联的第二CML锁存器的输出信号，第二CML锁存器在第一CML锁存器下游的串联点连接; 以及确定所述输出信号是否根据所述第一信号的改变而改变。

公开(公告)号：US20090027075A1

公开(公告)日：2009-01-29

申请号：US12189226

申请日：2008-08-11

申请人： Joseph O. Marsh ,  Jeremy Stephens ,  Charlie C. Hwang ,  James S. Mason ,  Huihao Xu ,  Matthew B. Baecher ,  Thomas J. Bardsley ,  Mark R. Taylor

发明人： Joseph O. Marsh ,  Jeremy Stephens ,  Charlie C. Hwang ,  James S. Mason ,  Huihao Xu ,  Matthew B. Baecher ,  Thomas J. Bardsley ,  Mark R. Taylor

IPC分类号： G01R31/28

CPC分类号： G01R31/3167 ,  G01R31/318544

摘要： A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal. The method of the present invention comprises digitally testing the differential driver circuit by activating a test enable signal, skewing the differential output termination impedance in response to the test enable signal, adjusting a voltage offset of the differential receiver circuit in response to the test enable signal, selecting a power level for the differential driver circuit in response to the test enable signal, enabling a decoder in response to the test enable signal, wherein the decoder activates only one segment of the differential driver circuit during any one test sequence, activating one of the segments for testing, stimulating the differential driver circuit with digital test patterns, receiving an output of the differential driver circuit by the differential receiver circuit, converting the received differential driver output to a single-ended signal, observing the single-ended signal; and deactivating the test enable signal.

摘要翻译： 使用基于数字扫描的测试方法测试模拟驱动器电路的电路和方法。 本发明的电路包括用于响应于测试使能信号产生信号的控制电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号并响应差分输入信号发送差分输出信号 以及由所述控制电路产生的信号，用于响应于由所述控制电路产生的信号而在所述差分驱动器电路的输出节点处产生差分终端阻抗的可编程终端阻抗电路以及用于从所述差分接收电路接收所述差分输出的差分接收电路 差分驱动器电路将差分输出信号转换为单端信号并传输单端信号，全部是响应于测试使能信号。 本发明的方法包括通过激活测试使能信号来数字测试差分驱动器电路，响应于测试使能信号偏移差动输出终​​端阻抗，响应于测试使能信号调整差分接收器电路的电压偏移 ，响应于所述测试使能信号选择所述差分驱动器电路的功率电平，使能够响应于所述测试使能信号的解码器，其中所述解码器在任何一个测试序列期间仅激活所述差分驱动器电路的一个部分， 用于测试的段，用数字测试图案刺激差分驱动器电路，通过差分接收器电路接收差分驱动器电路的输出，将接收到的差分驱动器输出转换为单端信号，观察单端信号; 并禁用测试使能信号。

公开(公告)号：US07466156B2

公开(公告)日：2008-12-16

申请号：US10708788

申请日：2004-03-25

申请人： Joseph O. Marsh ,  Jeremy Stephens ,  Charlie C. Hwang ,  James S. Mason ,  Huihao Xu ,  Matthew B. Baecher ,  Thomas J. Bardsley ,  Mark R. Taylor

发明人： Joseph O. Marsh ,  Jeremy Stephens ,  Charlie C. Hwang ,  James S. Mason ,  Huihao Xu ,  Matthew B. Baecher ,  Thomas J. Bardsley ,  Mark R. Taylor

IPC分类号： G01R31/02

CPC分类号： G01R31/3167 ,  G01R31/318544

摘要： A circuit of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention includes a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.

摘要翻译： 使用基于数字扫描的测试方法测试模拟驱动器电路的电路。 本发明的电路包括用于响应于测试使能信号产生信号的控制电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号并响应差分输入信号发送差分输出信号 以及由所述控制电路产生的信号，用于响应于由所述控制电路产生的信号而在所述差分驱动器电路的输出节点处产生差分终端阻抗的可编程终端阻抗电路以及用于从所述差分接收电路接收所述差分输出的差分接收电路 差分驱动器电路将差分输出信号转换为单端信号并传输单端信号，全部是响应于测试使能信号。

公开(公告)号：US07358787B2

公开(公告)日：2008-04-15

申请号：US11307923

申请日：2006-02-28

申请人： Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

发明人： Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

IPC分类号： H03K3/289

CPC分类号： H03K3/356043

摘要： A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the states of the pair of input differential data signals. A mode control device is operable to receive a mode control signal to operate the CML latch as a buffer or as a latch. In such way, when the mode control signal is inactive, the CML latch generates and latches the output signal at a timing determined by the at least one clock signal, and when the mode control signal is active the CML latch generates the output signal such that the output signal changes whenever the states of the pair of differential input data signals change.

摘要翻译： 提供了一种双用途电流模式逻辑（“CML”）锁存电路，其包括可操作以接收至少一对差分输入数据信号和至少一个时钟信号的CML锁存器。 CML锁存器可操作以根据输入差分数据信号对的状态产生至少一个输出信号。 模式控制装置可操作以接收模式控制信号以将CML锁存器作为缓冲器或锁存器操作。 以这种方式，当模式控制信号无效时，CML锁存器产生并以由至少一个时钟信号确定的定时锁存输出信号，并且当模式控制信号有效时，CML锁存器产生输出信号，使得 每当差分输入数据信号对的状态改变时，输出信号就会改变。

公开(公告)号：US07191305B2

公开(公告)日：2007-03-13

申请号：US10952269

申请日：2004-09-28

申请人： William D. Corti ,  Joseph O. Marsh ,  Michael Won

发明人： William D. Corti ,  Joseph O. Marsh ,  Michael Won

IPC分类号： G06F12/00

CPC分类号： G11C8/04

摘要： A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

摘要翻译： 公开了一种用于解码嵌入式DRAM（eDRAM）设备的存储器阵列地址的方法，该eDRAM器件被配置为与SDRAM存储器管理器一起操作。 在本发明的示例性实施例中，该方法包括在第一时间从存储器管理器接收一组行地址位。 随后，一组初始列地址位在稍后的时间从存储器管理器。 初始列地址位的集合被转换为一组转换的列地址位，并且行地址位集合和转换的列地址位的集合被同时用于访问eDRAM设备中期望的存储器位置。 eDRAM设备中期望的存储器位置具有对应于行地址位集合的值的行地址和对应于转换列地址位集合的值的列地址。

公开(公告)号：US06834360B2

公开(公告)日：2004-12-21

申请号：US09683091

申请日：2001-11-16

申请人： William D. Corti ,  Robert Kenny, Jr. ,  Joseph O. Marsh ,  Steven C. Parker ,  Frank X. Scanzano ,  Michael Won

发明人： William D. Corti ,  Robert Kenny, Jr. ,  Joseph O. Marsh ,  Steven C. Parker ,  Frank X. Scanzano ,  Michael Won

IPC分类号： G06F1100

CPC分类号： G06F11/3648 ,  G06F11/3636

摘要： An on-chip logic analysis (OCLA) system captures data processed by a signal processing logic core embedded in a single-chip-device (SOC) without interrupting operations of the signal processing logic core. The OCLA system includes a data capturing unit embedded in the SOC device to monitor the operations of the signal processing unit and determines whether the operations satisfy predetermined trigger conditions. Once the trigger condition is satisfied, the data capturing unit captures internal data from/to the signal processing unit and transfers to an external host system. The host system controls the operations of the data capturing unit. The host system provides the captured data to an user interface for testing and debugging the operations of the SOC signal processing device.

摘要翻译： 片上逻辑分析（OCLA）系统捕获由嵌入在单芯片器件（SOC）中的信号处理逻辑核处理的数据，而不中断信号处理逻辑核的操作。 OCLA系统包括嵌入在SOC装置中的数据捕获单元，用于监视信号处理单元的操作，并确定操作是否满足预定的触发条件。 一旦满足触发条件，数据捕获单元从信号处理单元捕获内部数据并将其传送到外部主机系统。 主机系统控制数据采集单元的操作。 主机系统将捕获的数据提供给用户界面，用于测试和调试SOC信号处理设备的操作。

公开(公告)号：US06834334B2

公开(公告)日：2004-12-21

申请号：US09940262

申请日：2001-08-28

申请人： William D. Corti ,  Joseph O. Marsh ,  Michael Won

发明人： William D. Corti ,  Joseph O. Marsh ,  Michael Won

IPC分类号： G06F1200

CPC分类号： G11C8/04

摘要： A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

摘要翻译： 公开了一种用于解码嵌入式DRAM（eDRAM）设备的存储器阵列地址的方法，该eDRAM器件被配置为与SDRAM存储器管理器一起操作。 在本发明的示例性实施例中，该方法包括在第一时间从存储器管理器接收一组行地址位。 随后，一组初始列地址位在稍后的时间从存储器管理器。 初始列地址位的集合被转换为一组转换的列地址位，并且行地址位集合和转换的列地址位的集合被同时用于访问eDRAM设备中期望的存储器位置。 eDRAM设备中期望的存储器位置具有对应于行地址位集合的值的行地址和对应于转换列地址位集合的值的列地址。

公开(公告)号：US07659740B2

公开(公告)日：2010-02-09

申请号：US12189226

申请日：2008-08-11

申请人： Joseph O. Marsh ,  Jeremy Stephens ,  Charlie C. Hwang ,  James S. Mason ,  Huihao Xu ,  Matthew B. Baecher ,  Thomas J. Bardsley ,  Mark R. Taylor

发明人： Joseph O. Marsh ,  Jeremy Stephens ,  Charlie C. Hwang ,  James S. Mason ,  Huihao Xu ,  Matthew B. Baecher ,  Thomas J. Bardsley ,  Mark R. Taylor

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/3167 ,  G01R31/318544

摘要： Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.

摘要翻译： 使用包括用于产生信号的控制电路的电路，用于接收差分输入信号的差分驱动器电路，放大差分输入信号和发送差分输出信号来实现模拟驱动器电路的数字测试，用于产生可编程终端阻抗电路 在差分驱动电路的输出节点处的差分终端阻抗，以及用于将差分输出信号转换为单端信号并发送单端信号的差分接收电路。 测试包括偏移差分输出终端阻抗，调整差分接收器电路电压偏移，选择差分驱动器电路功率电平，使得能够在每个测试序列仅激活一个差分驱动器电路段的解码器，激活段，激励差分驱动器电路 具有数字测试模式，接收差分驱动电路输出，将输出转换为单端信号，并观察单端信号。

公开(公告)号：US20080129329A1

公开(公告)日：2008-06-05

申请号：US12002878

申请日：2007-12-19

申请人： Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

发明人： Joseph O. Marsh ,  Joseph Natonio ,  James M. Wilson

IPC分类号： H03K19/003

CPC分类号： H03K3/356043

摘要： A method of testing connectivity through a plurality of dual purpose current mode logic (“CML”) latch circuits connected in a series is provided. Each of the CML latch circuits are operable to latch at least one output signal at a timing in accordance with at least one clock signal and having a mode control device for operating the CML latch circuit as a buffer amplifier when the at least one clock signal is inactive. The method comprises the steps of activating the mode control devices of each of the CML latches to operate each of the CML latches as a buffer; inputting a first signal to a first CML latch of the series; latching an output signal of a second CML latch of the series, the second CML latch being connected at a point in the series downstream from the first CML latch; and determining whether the output signal changes in accordance with a change in the first signal.

摘要翻译： 提供了通过串联连接的多个双用途电流模式逻辑（“CML”）锁存电路来测试连接性的方法。 每个CML锁存电路可操作以根据至少一个时钟信号在定时锁存至少一个输出信号，并具有一个模式控制装置，用于当至少一个时钟信号为 不活跃 该方法包括以下步骤：激活每个CML锁存器的模式控制装置，以操作每个CML锁存器作为缓冲器; 向所述系列的第一CML锁存器输入第一信号; 锁存串联的第二CML锁存器的输出信号，第二CML锁存器在第一CML锁存器下游的串联点连接; 以及确定所述输出信号是否根据所述第一信号的改变而改变。

公开(公告)号：US07265696B2

公开(公告)日：2007-09-04

申请号：US11272589

申请日：2005-11-10

申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Joseph O. Marsh ,  Steven J. Zier

发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  Joseph O. Marsh ,  Steven J. Zier

IPC分类号： H03M1/10

CPC分类号： H03M1/1076

摘要： In a first aspect, a method of testing an analog circuit is provided. The method includes (1) providing the analog circuit with a screening circuit adapted to cause the analog circuit to function like a logic gate during a test; and (2) applying digital signals to the analog circuit to test the analog circuit at a wafer level so as to detect a defect in one or more components of the analog circuit. Numerous other aspects are provided.