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161 条记录 (耗时 0.02 秒)

    Phase detector
    1.
    发明授权
    Phase detector 有权

    公开(公告)号：US09755653B2

    公开(公告)日：2017-09-05

    申请号：US14737603

    申请日：2015-06-12

    申请人： MEDIATEK Inc.

    发明人： Pang-Ning Chen ,  Yu-Li Hsueh ,  Pi-An Wu

    IPC分类号： H03L7/06 ,  H03L7/089 ,  H03K5/156 ,  H03K3/356 ,  H03L7/085

    CPC分类号： H03L7/089 ,  H03K3/356043 ,  H03K5/1565 ,  H03L7/085

    摘要： A phase detector including a first latch and a control circuit is provided. The first latch generates a first output signal and a second output signal in response to a phase difference between a first input signal and a second input signal. Each of the first and second output signals includes first phase information and second phase information of the phase difference. The control circuit generates a phase indicating signal in response to the first phase information of the phase difference. The phase indicating signal indicates a relative position between the first input signal and the second input signal.

    Current-controlled CMOS logic family
    2.
    发明授权
    Current-controlled CMOS logic family 有权
    电流控制CMOS逻辑系列

    公开(公告)号：US08823435B2

    公开(公告)日：2014-09-02

    申请号：US13654158

    申请日：2012-10-17

    申请人： Broadcom Corporation

    发明人： Armond Hairapetian

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356139 ,  H03K3/356043 ,  H03K3/3562 ,  H03K17/04 ,  H03K17/04106 ,  H03K17/04163 ,  H03K17/693 ,  H03K19/09432 ,  H03K19/215 ,  H03K2217/0036

    摘要： Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

    摘要翻译： 用于实现超高速电路的各种电路技术使用以常规CMOS工艺技术制造的电流控制CMOS（C3MOS）逻辑。 使用C3MOS技术来实现包括逆变器/缓冲器，电平移位器，NAND，NOR，XOR门，锁存器，触发器等的整个逻辑元件族。 通过将高速C3MOS逻辑与低功耗常规CMOS逻辑相结合，实现了每个电路应用的功耗和速度之间的最佳平衡。 组合的C3MOS / CMOS逻辑允许更多地集成诸如光纤通信系统中使用的高速收发器之类的电路。

    Bistable CML circuit
    3.
    发明授权
    Bistable CML circuit 有权
    双稳态CML电路

    公开(公告)号：US08378727B2

    公开(公告)日：2013-02-19

    申请号：US13166608

    申请日：2011-06-22

    申请人： Pratap Narayan Singh ,  Stéphane Le Tual

    发明人： Pratap Narayan Singh ,  Stéphane Le Tual

    IPC分类号： H03K3/00

    CPC分类号： H03K3/356043 ,  H03K3/012 ,  H03K3/356078

    摘要： A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.

    摘要翻译： 一种公共源电路，包括在施加电压的端子和电流源之间并联的两个分支，每个分支包括：电阻器和晶体管的串联关联，其连接点限定所述分支的输出端子; 将所述分支的输入端子连接到所述晶体管的控制端子的第一开关; 以及用于放大表示相对分支的输出端子上存在的电平的数据的可控级。

    DIFFERENTIAL LATCH, DIFFERENTIAL FLIP-FLOP, LSI, DIFFERENTIAL LATCH CONFIGURATION METHOD, AND DIFFERENTIAL FLIP-FLOP CONFIGURATION METHOD
    6.
    发明申请
    DIFFERENTIAL LATCH, DIFFERENTIAL FLIP-FLOP, LSI, DIFFERENTIAL LATCH CONFIGURATION METHOD, AND DIFFERENTIAL FLIP-FLOP CONFIGURATION METHOD 有权
    差分锁存器，差分FLIP-FLOP，LSI，差分锁存配置方法和差分FLIP-FLOP配置方法

    公开(公告)号：US20110133805A1

    公开(公告)日：2011-06-09

    申请号：US13029649

    申请日：2011-02-17

    申请人： Tomohiro HAYASHI

    发明人： Tomohiro HAYASHI

    IPC分类号： H03K3/356 ,  H03K3/00

    CPC分类号： H03K3/3562 ,  H03K3/356043

    摘要： A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is controlled by a reset signal; and a switching transistor that is connected to the gate electrode of the data holding transistor and is controlled by a switch signal, being an inverted version of the reset signal.

    摘要翻译： 一种包括数据保持晶体管的差分锁存器，所述差分锁存器包括：复位晶体管，其连接到所述数据保持晶体管的栅电极并由复位信号控制; 以及与数据保持晶体管的栅电极连接并由开关信号控制的开关晶体管，作为复位信号的反相形式。

    OSCILLATION SIGNAL GENERATOR FOR COMPENSATING FOR I/Q MISMATCH AND COMMUNICATION SYSTEM INCLUDING THE SAME
    7.
    发明申请
    OSCILLATION SIGNAL GENERATOR FOR COMPENSATING FOR I/Q MISMATCH AND COMMUNICATION SYSTEM INCLUDING THE SAME 有权
    振荡信号发生器，用于补偿I / Q误码和包括其中的通信系统

    公开(公告)号：US20110074482A1

    公开(公告)日：2011-03-31

    申请号：US12858833

    申请日：2010-08-18

    申请人： Jae Hong Chang

    发明人： Jae Hong Chang

    IPC分类号： H03H11/16

    CPC分类号： H03K5/15006 ,  H03B27/00 ,  H03K3/356043 ,  H04B1/0475 ,  H04B1/30

    摘要： An oscillation signal generator for compensating for an in-phase (I)/quadrature-phase (Q) mismatch and a communication system including the same are provided. The oscillation signal generator includes a first latch configured to generate an I oscillation signal, a second latch that is cross-coupled with the first latch and generates a Q oscillation signal, and a phase compensator connected to at least one of the first latch or the second latch. The phase compensator complementarily adjusts bias currents of the first and second I differential transistor pairs of the first latch and/or complementarily adjusts bias currents of the first and second Q differential transistor pairs of the second latch. Accordingly, the I/Q mismatch is compensated for without an additional device, so that the phase match between an I signal and a Q signal is improved in the communication system.

    摘要翻译： 提供了用于补偿同相（I）/正交相（Q）失配的振荡信号发生器和包括其的通信系统。 所述振荡信号发生器包括配置成产生I振荡信号的第一锁存器，与所述第一锁存器交叉耦合并产生Q振荡信号的第二锁存器，以及连接到所述第一锁存器或所述第一锁存器中的至少一个的相位补偿器， 第二个锁。 相位补偿器互补地调整第一锁存器的第一和第二I个差分晶体管对的偏置电流和/或互补地调整第二锁存器的第一和第二Q个差分晶体管对的偏置电流。 因此，在没有附加装置的情况下补偿I / Q不匹配，使得在通信系统中I信号和Q信号之间的相位匹配得到改善。

    Circuits for forming the inputs of a latch
    8.
    发明授权
    Circuits for forming the inputs of a latch 有权
    用于形成闩锁输入的电路

    公开(公告)号：US07884658B2

    公开(公告)日：2011-02-08

    申请号：US12060190

    申请日：2008-03-31

    申请人： Peter Kinget ,  Shih-an Yu

    发明人： Peter Kinget ,  Shih-an Yu

    IPC分类号： H03K3/356

    CPC分类号： H03K3/356043 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1293 ,  H03J2200/10 ,  H03K23/667 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/1976 ,  H03M7/3022

    摘要： Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal.

    摘要翻译： 提供了用于形成锁存器的输入的电路。 在一些实施例中，用于形成锁存器的输入的电路包括：在第一栅极端子处具有第一栅极端子，第一漏极端子，第一源极端子，第一栅极长度和第一共模电平的第一晶体管，其中 第一门极端子向锁存器提供数据输入; 以及在所述第二栅极端子处具有第二栅极端子，第二漏极端子，第二源极端子，第二栅极长度和第二共模电平的第二晶体管，其中所述第二栅极端子为所述锁存器提供时钟输入， 所述第二漏极端子耦合到所述第一源极端子，并且所述第一栅极长度和所述第二栅极长度的尺寸设定成使得所述第一共模型电平和所述第二共模电平基本相等。

    D flip-flop
    10.
    发明授权
    D flip-flop 失效
    D触发器

    公开(公告)号：US07405606B2

    公开(公告)日：2008-07-29

    申请号：US11397880

    申请日：2006-04-03

    申请人： Chi Wah Kok ,  Yee Ching Tam

    发明人： Chi Wah Kok ,  Yee Ching Tam

    IPC分类号： H03K3/289

    CPC分类号： H03K3/012 ,  H03K3/356043 ,  H03K3/356156

    摘要： A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a single switching transistor having a gate connected to the output of the flip-flop and the input of the inverter as its load. The clock gating circuit, which may comprise an XNOR gate, reduces the frequency of switching events by permitting clock pulses to pass into the master or slave stage only when the input and output of the flip-flop are at the same logical state.

    摘要翻译： 公开了具有降低的功率乘积或降低的时钟线电容的D触发器。 触发器包括半静态从站或主站，通过输入和输出具有时钟门控。 半静态从动级输出反相器和由单个开关晶体管组成的反馈元件，该开关晶体管具有连接到触发器的输出端的栅极和作为其负载的反相器的输入端。 可以包括XNOR门的时钟门控电路通过仅当触发器的输入和输出处于相同逻辑状态时才允许时钟脉冲进入主器件级或从器级，从而降低开关事件的频率。