公开(公告)号：US20090144525A1

公开(公告)日：2009-06-04

申请号：US12359113

申请日：2009-01-23

Applicant: Ken SHOEMAKER ,  Sailesh KOTTAPALLI ,  Kin-Kee SIT

Inventor： Ken SHOEMAKER ,  Sailesh KOTTAPALLI ,  Kin-Kee SIT

IPC: G06F9/38 ,  G06F15/76

CPC classification number: G06F9/3802 ,  G06F9/3851 ,  G06F9/3885

Abstract: An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly.

Abstract translation: 提供多线程处理器。 多线程处理器包括接收第一线程的第一指令获取单元和用于接收第二线程的第二指令获取单元。 耦合到指令提取单元和执行单元的多线程调度器。 多线程调度器确定执行单元的宽度，并且执行单元相应地执行线程。

公开(公告)号：US07401211B2

公开(公告)日：2008-07-15

申请号：US09751762

申请日：2000-12-29

Applicant: Sailesh Kottapalli ,  Udo Walterscheidt

Inventor： Sailesh Kottapalli ,  Udo Walterscheidt

IPC: G06F9/48 ,  G06F9/312

CPC classification number: G06F9/3851 ,  G06F9/3867

Abstract: In a multi-threaded processor, a long latency data dependent thread is flushed from the execution pipelines. Once the stalled thread is flushed, the non-stalling threads in the pipeline can continue their execution. Several resources are used to reduce this unwanted impact of stalls on the non-stalling threads. Also, these resources ensure that the earlier stalled thread, now flushed, is re-executed when the data dependency is resolved.

Abstract translation: 在多线程处理器中，从执行流水线刷新长时间数据相关的线程。 一旦停止的线程被刷新，流水线中的非停顿线程可以继续执行。 使用了几种资源来减少失速对非拖延线程的不必要的影响。 此外，这些资源确保当数据依赖关系解决时，重新执行早期已停止的线程，现在已刷新。

公开(公告)号：US07149880B2

公开(公告)日：2006-12-12

申请号：US09753764

申请日：2000-12-29

Applicant: Sailesh Kottapalli

Inventor： Sailesh Kottapalli

IPC: G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3867

Abstract: A system and method for a simultaneous multithreaded processor that reduces the number of hardware components necessary as well as the complexity of design over current systems is disclosed. As opposed to requiring individual storage elements for saving instruction pointer information for each re-steer logic component within a processor pipeline, the present invention allows for instruction pointer information of an inactive thread to be stored in a single, ‘inactive thread’ storage element until the thread becomes active again.

Abstract translation: 公开了一种用于同时多线程处理器的系统和方法，其减少了所需的硬件组件的数量以及当前系统上的设计的复杂性。 与在处理器流水线内为每个重新转向逻辑组件需要单独的存储元件来保存指令指针信息相反，本发明允许将一个非活动线程的指令指针信息存储在一个“非线程线程”存储元件中，直到 线程再次变为活动状态。

公开(公告)号：US20060143390A1

公开(公告)日：2006-06-29

申请号：US11026316

申请日：2004-12-29

Applicant: Sailesh Kottapalli

Inventor： Sailesh Kottapalli

IPC: G06F12/00

CPC classification number: G06F12/084 ,  G06F12/0864 ,  G06F12/126

Abstract: An apparatus and method for fairly accessing a shared cache with multiple resources, such as multiple cores, multiple threads, or both are herein described. A resource within a microprocessor sharing access to a cache is assigned a static portion of the cache and a dynamic portion. The resource is blocked from victimizing static portions assigned to other resources, yet, allowed to victimize the static portion assigned to the resource and the dynamically shared portion. If the resource does not access the cache enough times over a period of time, the static portion assigned to the resource is reassigned to the dynamically shared portion.

Abstract translation: 这里描述了用于公平地访问具有多个资源（例如多个核心，多个线程或两者）的多个资源的共享高速缓存的装置和方法。 分配对高速缓存的访问的微处理器内的资源被分配有高速缓存的静态部分和动态部分。 该资源被阻止从分配给其他资源的静态部分受到伤害，但是允许资源分配给动态共享部分的静态部分。 如果资源在一段时间内没有足够的时间访问缓存，则分配给资源的静态部分被重新分配给动态共享部分。

公开(公告)号：US20060101208A1

公开(公告)日：2006-05-11

申请号：US10985484

申请日：2004-11-09

Applicant: Sailesh Kottapalli

Inventor： Sailesh Kottapalli

IPC: G06F12/00

CPC classification number: G06F12/127

Abstract: A method and apparatus for supporting temporal data and non-temporal data memory accesses in a cache is disclosed. In one embodiment, a specially selected way in a set is generally used for non-temporal data memory accesses. A non-temporal flag may be associated with this selected way. In one embodiment, cache lines from memory accesses including a non-temporal hint may be generally placed into the selected way, and the non-temporal flag then set. When a temporal data cache line is to be loaded into a set, it may overrule the normal replacement method when the non-temporal flag is set, and be loaded into that selected way.

Abstract translation: 公开了一种用于支持高速缓存中的时间数据和非时间数据存储器访问的方法和装置。 在一个实施例中，集合中特别选择的方式通常用于非时间数据存储器访问。 非时间标志可以与该选择的方式相关联。 在一个实施例中，包括非时间提示的存储器访问的高速缓存行通常可以被放置成所选择的方式，然后设置非时间标志。 当时间数据高速缓存行被加载到集合中时，当设置非时间标志时，它可能会推翻正常的替换方法，并将其加载到所选择的方式中。

公开(公告)号：US20050138332A1

公开(公告)日：2005-06-23

申请号：US10739686

申请日：2003-12-17

Applicant: Sailesh Kottapalli ,  Richard Goe ,  Youngsoo Choi

Inventor： Sailesh Kottapalli ,  Richard Goe ,  Youngsoo Choi

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3861

Abstract: A method and apparatus for using result-speculative data under run-ahead speculative execution is disclosed. In one embodiment, the uncommitted target data from instructions being run-ahead executed may be saved into an advance data table. This advance data table may be indexed by the lines in the instruction buffer containing the instructions for run-ahead execution. When the instructions are re-executed subsequent to the run-ahead execution, valid target data may be retrieved from the advance data table and supplied as part of a zero-clock bypass to support parallel re-execution. This may achieve parallel execution of dependent instructions. In other embodiments, the advance data table may be content-addressable-memory searchable on target registers and supply target data to general speculative execution.

Abstract translation: 公开了一种在预先推测执行下使用结果推测数据的方法和装置。 在一个实施例中，来自正在执行的预定指令的未提交的目标数据可以被保存到提前数据表中。 该提前数据表可以由包含用于预先执行的指令的指令缓冲器中的行进行索引。 当在超前执行之后重新执行指令时，可以从提前数据表中检索有效的目标数据，并作为零时钟旁路的一部分提供以支持并行重新执行。 这可以实现依赖指令的并行执行。 在其他实施例中，提前数据表可以是内容寻址存储器，可在目标寄存器上搜索，并将目标数据提供给一般推测执行。

公开(公告)号：US20050050296A1

公开(公告)日：2005-03-03

申请号：US10650335

申请日：2003-08-28

Applicant: Sailesh Kottapalli ,  Nadeem Firasta

Inventor： Sailesh Kottapalli ,  Nadeem Firasta

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/1054 ,  G06F12/1036

Abstract: A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded processor searches a translation look-aside buffer in an attempt to match a virtual memory address. If no matching valid virtual memory address is found, a new translation is retrieved and the translation look-aside buffer is searched for a matching physical memory address. If a matching physical memory address is found, the old translation is overwritten with a new translation. The multi-threaded processor may execute switch on event multi-threading or simultaneous multi-threading. If simultaneous multi-threading is executed, then access rights for each thread is associated with the translation.

Abstract translation: 公开了一种允许多线程处理器使用翻译后备缓冲器在预先验证的高速缓存中的不同线程上共享页面的方法和系统。 多线程处理器搜索翻译后备缓冲区以尝试匹配虚拟内存地址。 如果没有找到匹配的有效虚拟内存地址，则检索新的翻译，并搜索匹配的物理内存地址的翻译后备缓冲区。 如果找到匹配的物理内存地址，则使用新的翻译覆盖旧的翻译。 多线程处理器可以执行切换事件多线程或同时多线程。 如果同时执行多线程，则每个线程的访问权限与翻译相关联。

公开(公告)号：US10204049B2

公开(公告)日：2019-02-12

申请号：US13808595

申请日：2012-01-06

Applicant: Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Sailesh Kottapalli ,  Ganesh Kumar ,  Henk G. Neefs ,  Neil J. Achtman ,  Bongjin Jung

Inventor： Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Sailesh Kottapalli ,  Ganesh Kumar ,  Henk G. Neefs ,  Neil J. Achtman ,  Bongjin Jung

IPC: G06F12/084 ,  G06F12/0817

Abstract: Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.

公开(公告)号：US20150006834A1

公开(公告)日：2015-01-01

申请号：US13931875

申请日：2013-06-29

Applicant: Subramanya R. DULLOOR ,  Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Richard A. UHLIG ,  Robert S. CHAPPELL ,  Joseph NUZMAN ,  Kai CHENG ,  Sailesh KOTTAPALLI ,  Yen-Cheng LIU ,  Mohan KUMAR ,  Raj K. RAMANUJAN ,  Glenn J. HINTON

Inventor： Subramanya R. DULLOOR ,  Sanjay KUMAR ,  Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Richard A. UHLIG ,  Robert S. CHAPPELL ,  Joseph NUZMAN ,  Kai CHENG ,  Sailesh KOTTAPALLI ,  Yen-Cheng LIU ,  Mohan KUMAR ,  Raj K. RAMANUJAN ,  Glenn J. HINTON

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0671 ,  G06F13/1668

Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.

Abstract translation: 描述了用于在持久存储器架构中的存储耐久性和排序的装置和方法。 例如，方法的一个实施例包括：对识别至少一个持久存储器设备的一个或多个地址执行至少一个存储操作，所述存储操作使一个或多个存储器控制器将数据存储在所述至少一个持久存储器设备中; 向所述一个或多个存储器控制器发送请求消息，指示所述存储器控制器确认所述存储操作被成功地提交给所述至少一个持久存储器设备; 确保在所述一个或多个存储器控制器处，至少在请求消息时接收到的所有未决存储操作将被提交给持久存储器设备; 以及从所述一个或多个存储器控制器发送指示所述存储操作被成功地提交给所述持久存储器设备的响应消息。

公开(公告)号：US20140281270A1

公开(公告)日：2014-09-18

申请号：US13835862

申请日：2013-03-15

Applicant: Henk G. Neefs ,  Ganesh Kumar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Sailesh Kottapalli ,  Jeffrey S. Wilder

Inventor： Henk G. Neefs ,  Ganesh Kumar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Sailesh Kottapalli ,  Jeffrey S. Wilder

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F12/0817 ,  G06F12/082

Abstract: Methods and apparatus relating to directory based coherency to improve input/output write bandwidth in scalable systems are described. In one embodiment, a first agent receives a request to write data from a second agent via a link and logic causes the first agent to write the directory state to an Input/Output Directory Cache (IODC) of the first agent. Additionally, the logic causes the second agent to send data from a modified state to an exclusive state using write back to the first agent, while allowing the data to remain cached exclusively in the second agent and also enabling the deallocation of the IODC entry in the first agent. Other embodiments are also disclosed.

Abstract translation: 描述了与基于目录的一致性相关的方法和装置，以改善可扩展系统中的输入/输出写入带宽。 在一个实施例中，第一代理接收经由链路从第二代理程序写入数据的请求，并且逻辑使得第一代理将目录状态写入第一代理的输入/输出目录高速缓存（IODC）。 此外，逻辑使得第二代理使用回写到第一代理将数据从修改状态发送到独占状态，同时允许数据保持高速缓存在第二代理中，并且还允许在I / 第一代理 还公开了其他实施例。