公开(公告)号：US20140115274A1

公开(公告)日：2014-04-24

申请号：US14142044

申请日：2013-12-27

申请人： SAILESH KOTTAPALLI ,  HENK G. NEEFS ,  RAHUL PAL ,  MANOJ K. ARORA ,  DHEEMANTH NAGARAJ

发明人： SAILESH KOTTAPALLI ,  HENK G. NEEFS ,  RAHUL PAL ,  MANOJ K. ARORA ,  DHEEMANTH NAGARAJ

IPC分类号： G06F12/08

CPC分类号： G06F12/0833 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/4265 ,  G06F2212/621 ,  G06F2212/622

摘要： In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，确定与存储器位置相关联的目录条目是否指示该信息不存在于远程高速缓存代理中，如果是，则将该信息从存储器 关于读取请求的窥探处理之前的第一高速缓存代理的位置被完成。 描述和要求保护其他实施例。

公开(公告)号：US20130311821A1

公开(公告)日：2013-11-21

申请号：US13996717

申请日：2012-03-30

申请人： Brian S. Morris ,  Sailesh Kottapalli

发明人： Brian S. Morris ,  Sailesh Kottapalli

IPC分类号： G06F11/20

CPC分类号： G06F11/2094 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/20 ,  G06F2201/815

摘要： Systems and techniques for virtual device sharing. A failure of one of a plurality of memory devices corresponding to a first rank in a memory system is detected. The memory system has a plurality of ranks, each rank having a plurality of memory devices used to store a cache line. A portion of the cache line corresponding to the failed memory device is stored in a memory device in a second rank in the memory system and the remaining portion of the cache line in the first rank of the memory system.

摘要翻译： 用于虚拟设备共享的系统和技术。 检测到与存储器系统中的第一等级对应的多个存储器件中的一个的故障。 存储器系统具有多个等级，每个等级具有用于存储高速缓存行的多个存储器件。 对应于故障存储器件的高速缓存线的一部分被存储在存储器系统中的第二等级的存储器件中，并且存储器系统的第一级中的高速缓存行的剩余部分被存储。

公开(公告)号：US20130007046A1

公开(公告)日：2013-01-03

申请号：US13175772

申请日：2011-07-01

申请人： Allen J. Baum ,  Sailesh Kottapalli ,  Vedaraman Geetha

发明人： Allen J. Baum ,  Sailesh Kottapalli ,  Vedaraman Geetha

IPC分类号： G06F17/30

CPC分类号： G06F13/4022

摘要： Methods and apparatus relating to dynamically routing data responses directly to a requesting processor core are described. In one embodiment, data returned in response to a data request is to be directly transmitted to a requesting agent based on information stored in a route back table. Other embodiments are also disclosed.

摘要翻译： 描述了将数据响应直接动态地路由到请求处理器核心的方法和装置。 在一个实施例中，响应于数据请求返回的数据将基于存储在路由表中的信息直接发送到请求代理。 还公开了其他实施例。

公开(公告)号：US20120047333A1

公开(公告)日：2012-02-23

申请号：US12860340

申请日：2010-08-20

申请人： SAILESH KOTTAPALLI ,  Henk G. Neefs ,  Rahul Pal ,  Manoj K. Arora ,  Dheemanth Nagaraj

发明人： SAILESH KOTTAPALLI ,  Henk G. Neefs ,  Rahul Pal ,  Manoj K. Arora ,  Dheemanth Nagaraj

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0833 ,  G06F12/0817 ,  G06F12/0822 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/4265 ,  G06F2212/621 ,  G06F2212/622

摘要： In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，确定与存储器位置相关联的目录条目是否指示该信息不存在于远程高速缓存代理中，如果是，则将该信息从存储器 关于读取请求的窥探处理之前的第一高速缓存代理的位置被完成。 描述和要求保护其他实施例。

公开(公告)号：US20110252203A1

公开(公告)日：2011-10-13

申请号：US13168171

申请日：2011-06-24

申请人： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

发明人： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

IPC分类号： G06F12/08

CPC分类号： G06F9/528 ,  G06F9/3834 ,  G06F9/544

摘要： The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

公开(公告)号：US20110173634A1

公开(公告)日：2011-07-14

申请号：US13069684

申请日：2011-03-23

申请人： Sailesh Kottapalli ,  John H. Crawford

发明人： Sailesh Kottapalli ,  John H. Crawford

IPC分类号： G06F9/46

CPC分类号： G06F9/522 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857

摘要： In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。 以这种方式，当所有线程都到达障碍物时，建立同步。 在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。 描述和要求保护其他实施例。

公开(公告)号：US07500240B2

公开(公告)日：2009-03-03

申请号：US10047809

申请日：2002-01-15

申请人： Ken Shoemaker ,  Sailesh Kottapalli ,  Kin-Kee Sit

发明人： Ken Shoemaker ,  Sailesh Kottapalli ,  Kin-Kee Sit

IPC分类号： G06F9/46 ,  G06F15/00 ,  G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3851 ,  G06F9/3885

摘要： An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly.

摘要翻译： 提供多线程处理器。 多线程处理器包括接收第一线程的第一指令获取单元和用于接收第二线程的第二指令获取单元。 耦合到指令提取单元和执行单元的多线程调度器。 多线程调度器确定执行单元的宽度，并且执行单元相应地执行线程。

公开(公告)号：US20080215864A1

公开(公告)日：2008-09-04

申请号：US11638315

申请日：2006-12-12

申请人： Sailesh Kottapalli

发明人： Sailesh Kottapalli

IPC分类号： G06F9/312

CPC分类号： G06F9/3851 ,  G06F9/3867

摘要： A simultaneous multithreaded processor that reduces the number of hardware components necessary as well as the complexity of design over current systems is disclosed. As opposed to requiring individual storage elements for saving instruction pointer information for each re-steer logic component within a processor pipeline, the present invention allows for instruction pointer information of an inactive thread to be stored in a single, ‘inactive thread’ storage element until the thread becomes active again.

摘要翻译： 公开了一种同时多线程处理器，其减少了所需的硬件组件的数量以及当前系统上的设计的复杂性。 与在处理器流水线内为每个重新转向逻辑组件需要单独的存储元件来保存指令指针信息相反，本发明允许将一个非活动线程的指令指针信息存储在一个“非线程线程”存储元件中，直到 线程再次变为活动状态。

公开(公告)号：US20050066151A1

公开(公告)日：2005-03-24

申请号：US10666343

申请日：2003-09-19

申请人： Sailesh Kottapalli

发明人： Sailesh Kottapalli

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/3017 ,  G06F9/30072 ,  G06F9/384

摘要： A method and apparatus for permitting out-of-order execution of predicated instructions is disclosed. In one embodiment, a predicated instruction may be decoded into a related predicated instruction and a move instruction contingent on the complementary value of the predicate of the predicated instruction. The destination register of both the related predicated instruction and the move instruction may be mapped to the same physical register, and only one of the two instructions may update machine state with its results.

摘要翻译： 公开了一种用于允许无序执行预定指令的方法和装置。 在一个实施例中，预测指令可以被解码成相关的预测指令和移动指令，这取决于预测指令的谓词的互补值。 相关的预测指令和移动指令的目标寄存器可以被映射到相同的物理寄存器，并且两个指令中的仅一个可以用其结果来更新机器状态。

公开(公告)号：US10387151B2

公开(公告)日：2019-08-20

申请号：US13250223

申请日：2011-09-30

申请人： Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

发明人： Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F12/06 ,  G06F12/08 ,  G06F9/345

摘要： Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.