公开(公告)号：US08648889B2

公开(公告)日：2014-02-11

申请号：US12085529

申请日：2006-06-28

申请人： Yuhko Hisada ,  Ryohki Itoh ,  Takaharu Yamada ,  Hideki Morii ,  Takayuki Mizunaga

发明人： Yuhko Hisada ,  Ryohki Itoh ,  Takaharu Yamada ,  Hideki Morii ,  Takayuki Mizunaga

IPC分类号： G09G5/02

CPC分类号： G09G3/3648 ,  G09G3/2003 ,  G09G3/3607 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2300/0465 ,  G09G2320/0209 ,  G09G2320/0233 ,  G09G2320/0242 ,  G09G2340/06

摘要： In one embodiment of the present invention, in an even-numbered signal line group, the arrangement sequence of the first and second signal lines is reversed between in a display area and in a non-display area, and the same goes for the arrangement sequence of the third and fourth signal lines. The ends of the first to sixteenth signal lines in the non-display area are connected to the first to sixteenth individual drivers, respectively. An odd-numbered individual driver and an even-numbered individual driver each output a corresponding one of drive signals of opposite polarity. Thus, the polarities of subpixels of the same color arranged in a first direction D1 (horizontal direction) differ between the subpixels connected to the odd-numbered signal line group and the subpixels connected to the even-numbered signal line group. That is, all of the subpixels having the same color arranged in the horizontal direction do not have the same polarity. This helps reduce a horizontal shadow.

摘要翻译： 在本发明的一个实施例中，在偶数信号线组中，第一和第二信号线的排列顺序在显示区域和非显示区域之间是相反的，并且排列顺序也相同 的第三和第四信号线。 非显示区域中的第一至第十六信号线的端部分别连接到第一至第十六个单独驱动器。 奇数个体驱动器和偶数个别驱动器各自输出相反极性的相应驱动信号。 因此，连接到奇数编号信号线组的子像素与连接到偶数信号线组的子像素之间，沿第一方向D1（水平方向）布置的相同颜色的子像素的极性不同。 也就是说，具有沿水平方向布置的相同颜色的所有子像素不具有相同的极性。 这有助于减少水平阴影。

公开(公告)号：US08531224B2

公开(公告)日：2013-09-10

申请号：US13501215

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

IPC分类号： H03K3/00

CPC分类号： G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver.In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

摘要翻译： 目的是在单片门驱动器内的移位寄存器中抑制时钟下降周期，同时抑制电路面积的增加，电流消耗的增加和成本增加，而不产生异常操作。 在基于提供给奇数级的两相时钟信号（GCK1，GCK3）和提供给奇数级的两相时钟信号（GCK2，GCK4）的四相时钟信号的移位寄存器（410）中， 到相位相互偏移90度的偶数级，当第一节点的电位处于高电平时，第一时钟（CKA）的电位作为扫描信号（GOUT）的电位出现 水平，在每个阶段。 在这种配置中，基于从前级输出的扫描信号的脉冲将每级中包括的第一节点的电位设置为高电平，并且基于扫描信号的脉冲将其设置为低电平 在有关阶段后从第三阶段输出。

公开(公告)号：US20130027104A1

公开(公告)日：2013-01-31

申请号：US13637647

申请日：2011-01-26

申请人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga

发明人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga

IPC分类号： H03H11/16

CPC分类号： H03K19/0175

摘要： An object of the present invention is to provide a level shift IC with a reduced number of input signals over the conventional case. A level shift IC includes an amplitude converting unit including four level shifters; and a different-phase signal generating unit at a stage previous to the amplitude converting unit, including delay circuits. The different-phase signal generating unit generates, by the delay circuits, first and second delayed input signals from first and second input signals of different phases. Therefore, four input signals of different phases are obtained, and the amplitude converting unit increases the amplitudes of the input signals by the amplitude converting unit and thereby generates first to fourth output signals with different phases and increased amplitudes.

摘要翻译： 本发明的目的是提供一种在常规情况下具有减少的输入信号数量的电平转换IC。 电平移位IC包括具有四个电平移位器的振幅转换单元; 以及在振幅转换单元之前的阶段的不同相位信号生成单元，包括延迟电路。 不同相位信号产生单元由延迟电路产生来自不同相位的第一和第二输入信号的第一和第二延迟输入信号。 因此，获得不同相位的四个输入信号，并且幅度转换单元通过幅度转换单元增加输入信号的幅度，从而产生具有不同相位和增加幅度的第一至第四输出信号。

公开(公告)号：US20110001732A1

公开(公告)日：2011-01-06

申请号：US12735771

申请日：2008-10-22

申请人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane ,  Shinya Tanaka ,  Hajime Imai ,  Tetsuo Kikuchi

发明人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane ,  Shinya Tanaka ,  Hajime Imai ,  Tetsuo Kikuchi

IPC分类号： G09G5/00 ,  G11C19/36

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： In at least one embodiment, each of stages connected in cascade includes a first circuit which causes a predetermined section in a corresponding one of the stages to be connected to a low-potential power source, the first circuit being constituted by TFTs, a first type of clock signal being used as a signal which is transferred to an output terminal of each of the stages so as to be outputted as an output signal, a second type of clock signal being used as a signal which drives the first circuit. With the arrangement, it is possible to realize a shift register circuit that is capable of further suppressing a shift phenomenon of a threshold voltage in each of the TFTs.

摘要翻译： 在至少一个实施例中，级联连接的每个级包括第一电路，其使相应级中的预定部分连接到低电位电源，第一电路由TFT构成，第一类型 时钟信号被用作被传送到每个级的输出端的信号，以作为输出信号输出，第二类型的时钟信号用作驱动第一电路的信号。 通过该结构，可以实现能够进一步抑制各TFT的阈值电压的偏移现象的移位寄存器电路。

公开(公告)号：US20100321372A1

公开(公告)日：2010-12-23

申请号：US12735658

申请日：2008-10-20

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： Each stage of first and second shift registers outputs a scan pulse by transferring a clock pulse of a clock signal supplied through a first clock input terminal. A first transistor is provided in at least one embodiment so as to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, and the first transistor has a gate that receives a clock signal supplied through a second clock input terminal. Two clock signals supplied to the first shift register and two clock signals supplied to the second shift register are different from each other in timings of their clock pulses. This realizes a display device capable of curbing the phenomenon in which a threshold voltage of a sink-down transistor is shifted, while sinking the gate line voltage down.

摘要翻译： 第一和第二移位寄存器的每一级通过传送通过第一时钟输入端提供的时钟信号的时钟脉冲来输出扫描脉冲。 在至少一个实施例中提供第一晶体管，以将与各个级相对应的扫描信号线与扫描脉冲的低电平电源连接和断开，并且第一晶体管具有接收时钟的栅极 信号通过第二时钟输入端子提供。 提供给第一移位寄存器的两个时钟信号和提供给第二移位寄存器的两个时钟信号在其时钟脉冲的定时中彼此不同。 这实现了能够抑制下沉晶体管的阈值电压移位的现象的显示装置，同时使栅极线电压降低。

公开(公告)号：US20090115910A1

公开(公告)日：2009-05-07

申请号：US11921402

申请日：2006-05-19

申请人： Masakazu Takeuchi ,  Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga

发明人： Masakazu Takeuchi ,  Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga

IPC分类号： H04N9/64

CPC分类号： H04N5/202 ,  H04N9/646 ,  H04N9/69

摘要： In one embodiment of the present invention, a video signal processing method is disclosed wherein video correction data is read from a ROM and written into an LUT, and the video correction data written in the LUT is used to perform data correction of an externally inputted video signal. The video correction data written in the LUT is updated during the horizontal blanking interval of the video signal.

摘要翻译： 在本发明的一个实施例中，公开了一种视频信号处理方法，其中从ROM中读取视频校正数据并将其写入LUT，并且使用写入LUT的视频校正数据来执行外部输入视频的数据校正 信号。 写入LUT中的视频校正数据在视频信号的水平消隐间隔期间被更新。

公开(公告)号：US20090040243A1

公开(公告)日：2009-02-12

申请号：US12085529

申请日：2006-06-28

申请人： Yuhko Hisada ,  Ryohki Itoh ,  Takaharu Yamada ,  Hideki Morii ,  Takayuki Mizunaga

发明人： Yuhko Hisada ,  Ryohki Itoh ,  Takaharu Yamada ,  Hideki Morii ,  Takayuki Mizunaga

IPC分类号： G06F3/038

CPC分类号： G09G3/3648 ,  G09G3/2003 ,  G09G3/3607 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2300/0465 ,  G09G2320/0209 ,  G09G2320/0233 ,  G09G2320/0242 ,  G09G2340/06

摘要： In one embodiment of the present invention, in an even-numbered signal line group, the arrangement sequence of the first and second signal lines is reversed between in a display area and in a non-display area, and the same goes for the arrangement sequence of the third and fourth signal lines. The ends of the first to sixteenth signal lines in the non-display area are connected to the first to sixteenth individual drivers, respectively. An odd-numbered individual driver and an even-numbered individual driver each output a corresponding one of drive signals of opposite polarity. Thus, the polarities of subpixels of the same color arranged in a first direction D1 (horizontal direction) differ between the subpixels connected to the odd-numbered signal line group and the subpixels connected to the even-numbered signal line group. That is, all of the subpixels having the same color arranged in the horizontal direction do not have the same polarity. This helps reduce a horizontal shadow.

摘要翻译： 在本发明的一个实施例中，在偶数信号线组中，在显示区域和非显示区域中，第一和第二信号线的排列顺序相反，并且排列顺序也相同 的第三和第四信号线。 非显示区域中的第一至第十六信号线的端部分别连接到第一至第十六个单独驱动器。 奇数个体驱动器和偶数个别驱动器各自输出相反极性的相应驱动信号。 因此，连接到奇数编号信号线组的子像素与连接到偶数信号线组的子像素之间，沿第一方向D1（水平方向）布置的相同颜色的子像素的极性不同。 也就是说，具有沿水平方向布置的相同颜色的所有子像素不具有相同的极性。 这有助于减少水平阴影。