公开(公告)号：US20140306948A1

公开(公告)日：2014-10-16

申请号：US14364090

申请日：2012-08-09

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kazuya Nakaminami ,  Satoshi Horiuchi

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kazuya Nakaminami ,  Satoshi Horiuchi

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3648 ,  G09G3/3696 ,  G09G2310/0286 ,  G09G2330/02 ,  G09G2330/027

摘要： Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device.In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged. In the second discharge step, the clear signal (H_CLR) is set at the high level, and electric charges on floating nodes in each of the bistable circuits are discharged.

摘要翻译： 提供：当电源关闭时能够快速去除面板中的残余电荷的液晶显示装置，特别是适用于采用IGZO-GDM的情况的液晶显示装置。 以及液晶显示装置的驱动方法。 在液晶显示装置中，当检测到电源的OFF状态时，执行包括初始化步骤，第一放电步骤和第二放电步骤的电源OFF序列。 在初始化步骤中，仅将GDM信号中的清除信号（H_CLR）设置为高电平，并且构成移位寄存器的双稳态电路的状态被初始化。 在第一放电步骤中，只有GDM信号中的清除信号（H_CLR）被设置为低电平，所有栅极总线被转换到选择状态，并且像素形成部分中的电荷被放电。 在第二放电步骤中，清零信号（H_CLR）被设置为高电平，并且每个双稳态电路中的浮动节点上的电荷被放电。

公开(公告)号：US20130057598A1

公开(公告)日：2013-03-07

申请号：US13698094

申请日：2011-04-18

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

IPC分类号： G09G5/10

CPC分类号： G02F1/136286 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/0426 ,  G09G2300/0439

摘要： The present invention provides a display panel having decreased cost and current consumption by decreasing the number of data signal lines from the conventional number, a display device including the display panel, and a method of driving the display device.Each pixel formation portion (10) included in a display unit (200) of a display device is configured to arrange three sub-pixel formation portions (1r, 1g, 1b) for forming sub-pixels of mutually different color components in a data signal line extension direction. Each one data signal line (30) is arranged between a sub-pixel formation portion vertical string (3) in an odd-order from a front of a scanning signal line extension direction and a sub-pixel formation portion vertical string (3) adjacent to the sub-pixel formation portion vertical string (3) at the back of the scanning signal line extension direction. Sub-pixel formation portion vertical strings (3, 3) positioned at both sides of each data signal line (30) are connected to the data signal line. Each one scanning signal line (40) is arranged at both sides of a sub-pixel formation portion in a data signal line extension direction. Mutually adjacent sub-pixel formation portion vertical strings (3, 3) are connected to mutually different scanning signal line (40).

摘要翻译： 本发明提供一种显示面板，其通过从常规数量减少数据信号线的数量，包括显示面板的显示装置和驱动显示装置的方法而具有降低的成本和电流消耗。 包括在显示装置的显示单元（200）中的每个像素形成部分（10）被配置为布置用于在数据信号中形成彼此不同的颜色分量的子像素的三个子像素形成部分（1r，1g，1b） 线延伸方向。 每个数据信号线（30）被布置在从扫描信号线延伸方向的前面开始的奇数级的子像素形成部垂直串（3）和相邻的子像素形成部垂直串（3）之间 到扫描信号线延伸方向后面的子像素形成部分垂直线（3）。 位于每个数据信号线（30）两侧的子像素形成部分垂直弦线（3,3）连接到数据信号线。 每个扫描信号线（40）布置在数据信号线延伸方向上的子像素形成部分的两侧。 相互相邻的子像素形成部垂直串（3,3）连接到相互不同的扫描信号线（40）。

公开(公告)号：US20120200544A1

公开(公告)日：2012-08-09

申请号：US13501215

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

IPC分类号： G06F3/038 ,  G11C19/28

CPC分类号： G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： In a shift register that operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock appears as a potential of a scanning signal, when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

摘要翻译： 在基于四相时钟信号工作的移位寄存器中，包括提供给奇数级的两相时钟信号和提供给偶数级的两相时钟信号，其中相位偏移90 在第一节点的电位处于高电平时，第一时钟的电位在扫描信号的电位下显现。 在这种配置中，基于从前级输出的扫描信号的脉冲将每级中包括的第一节点的电位设置为高电平，并且基于扫描信号的脉冲将其设置为低电平 在有关阶段后从第三阶段输出。

公开(公告)号：US20110134090A1

公开(公告)日：2011-06-09

申请号：US12737649

申请日：2009-05-27

申请人： Akihisa Iwamoto ,  Takayuki Mizunaga ,  Hideki Morii ,  Yuuki Ohta ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Takayuki Mizunaga ,  Hideki Morii ,  Yuuki Ohta ,  Kei Ikuta

IPC分类号： G06F3/038 ,  G11C19/28

CPC分类号： G11C19/184 ,  G09G3/3677 ,  G09G2310/0286 ,  G11C19/28

摘要： A control section prepares a control signal and supplies the control signal to a control terminal of a first switching element, the control signal causing the first switching element to turn on in accordance with a non-active voltage level of a storage node and an active voltage level of a second clock signal which active voltage level is obtained in a period in which the second clock signal is active.

摘要翻译： 控制部分准备控制信号，并将控制信号提供给第一开关元件的控制端，该控制信号使得第一开关元件根据存储节点的非有效电压电平和有源电压而导通 在第二时钟信号有效的时段中得到有效电压电平的第二时钟信号的电平。

公开(公告)号：US20110018845A1

公开(公告)日：2011-01-27

申请号：US12736121

申请日：2008-12-17

申请人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Masahiro Hirokane ,  Yuuki Ohta

发明人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Masahiro Hirokane ,  Yuuki Ohta

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2330/025 ,  G11C19/184 ,  G11C19/28

摘要： A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

摘要翻译： 显示面板驱动电路包括由分阶段连接的单元电路构成的移位寄存器。 单位电路分别产生信号线选择信号，这些信号线选择信号在相应的特定时间段内被激活以形成相应的脉冲，并且从相应的单位电路依次从 第一阶段直到结束阶段。 在至少一个实施例中，每个单元电路接收（i）基于从显示面板驱动电路的外部接收的同步信号产生的时钟信号，（ii）基于同步信号产生的起始脉冲信号或信号 在与其自身的阶段不同的阶段中产生的线选择信号，以及（iii）清除信号。 在同步信号中包含异常的情况下，清除信号被激活，并且在随后的垂直扫描期间开始之前没有脉冲从移位寄存器输出。 这种配置实现了一种显示面板驱动电路，其防止显示无序或者抑制给予电源的负载增加，每个电源在同步信号中包括异常的情况下发生。

公开(公告)号：US20120194489A1

公开(公告)日：2012-08-02

申请号：US13501198

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

IPC分类号： G06F3/038 ,  G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

摘要翻译： 构成移位寄存器的各级包括用于增加基于第一时钟（CKA）的扫描信号的电位的输出控制薄膜晶体管，用于增加连接到栅极的第一节点的电位的两个薄膜晶体管 基于从前级/后级输出的扫描信号的输出控制薄膜晶体管的端子和用于降低第一节点的电位的两个薄膜晶体管，基于从 在有关阶段之后的第三阶段。 移位寄存器基于四相时钟信号进行操作，包括提供给奇数级的两相时钟信号和提供给偶数级的两相时钟信号，其中相位偏移90度 彼此。

公开(公告)号：US20100325466A1

公开(公告)日：2010-12-23

申请号：US12735708

申请日：2008-12-04

申请人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Masahiro Hirokane

发明人： Yuuki Ohta ,  Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Masahiro Hirokane

IPC分类号： G06F1/04 ,  G06F1/12 ,  G02F1/1333

CPC分类号： G09G3/3677 ,  G11C19/28

摘要： In at least one embodiment, a display panel drive circuit including a shift register including unit circuits connected in cascade, each of the unit circuits outputting a signal line selection signal, is configured such that: each of the unit circuits receives a clock signal and either a signal line selection signal outputted from another-stage unit circuit or a start pulse signal; and the clock signal has a rising portion which is caused by activation of the clock signal and which is sloped or a falling portion which is caused by activation of the clock signal and which is sloped. With the configuration, it is possible to realize a display panel drive circuit and a display panel driving method each of which hardly causes a poor gate-on pulse signal (which causes unevenness in electric potential during inactivation, for example.

摘要翻译： 在至少一个实施例中，包括移位寄存器的显示面板驱动电路，其包括级联连接的单元电路，输出信号线选择信号的每个单位电路被配置为：每个单元电路接收时钟信号， 从另一级单元电路输出的信号线选择信号或起始脉冲信号; 并且时钟信号具有由时钟信号的激活引起的上升部分，并且是由于时钟信号的激活而导致的倾斜的下降部分和倾斜的。 通过这样的结构，能够实现显示面板驱动电路和显示面板驱动方法，每个显示面板驱动电路和显示面板驱动方法几乎不会导致差的导通脉冲信号（例如在失活期间导致电位不均匀）。

公开(公告)号：US09293094B2

公开(公告)日：2016-03-22

申请号：US14237677

申请日：2012-08-03

申请人： Hideki Morii ,  Akihisa Iwamoto ,  Satoshi Horiuchi ,  Takayuki Mizunaga ,  Kazuya Nakaminami

发明人： Hideki Morii ,  Akihisa Iwamoto ,  Satoshi Horiuchi ,  Takayuki Mizunaga ,  Kazuya Nakaminami

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/3677 ,  G09G2330/027

摘要： The invention provides a liquid crystal display device that includes an IGZO-GDM which can quickly remove a residual charge in a panel when the power supply is turned off, and a driving method of the liquid crystal display device. Each bistable circuit that configures a shift register includes a thin film transistor TI for increasing a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin film transistor TI, a thin film transistor TC for lowering a potential of the region netA, and a region netB connected to a gate terminal of the thin film transistor TC. In such a configuration, a power supply off sequence includes a display off sequence and a gate off sequence. The gate off sequence includes at least a gate-bus-line discharge step (t14 to t15), a netB discharge step (t15 to t16), and a netA discharge step (t16 to t17).

摘要翻译： 本发明提供了一种液晶显示装置，其包括IGART-GDM，其可以在电源关闭时快速去除面板中的残留电荷，以及液晶显示装置的驱动方法。 配置移位寄存器的每个双稳态电路包括用于基于第一时钟增加输出端子的电位的薄膜晶体管TI，连接到薄膜晶体管TI的栅极端子的区域netA，用于降低的薄膜晶体管TC 区域netA的电位和连接到薄膜晶体管TC的栅极端子的区域netB。 在这种配置中，电源断开序列包括显示关闭序列和关闭序列。 栅极截止序列至少包括栅极总线放电步骤（t14至t15），netB放电步骤（t15至t16）和netA放电步骤（t16至t17）。

公开(公告)号：US08952880B2

公开(公告)日：2015-02-10

申请号：US12736121

申请日：2008-12-17

申请人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Masahiro Hirokane ,  Yuuki Ohta

发明人： Takayuki Mizunaga ,  Hideki Morii ,  Akihisa Iwamoto ,  Masahiro Hirokane ,  Yuuki Ohta

IPC分类号： G09G3/36 ,  G11C19/00 ,  G11C19/18 ,  G11C19/28

CPC分类号： G09G3/3677 ,  G09G2310/0286 ,  G09G2330/025 ,  G11C19/184 ,  G11C19/28

摘要： A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

摘要翻译： 显示面板驱动电路包括由分阶段连接的单元电路构成的移位寄存器。 单位电路分别产生信号线选择信号，这些信号线选择信号在相应的特定时间段内被激活以形成相应的脉冲，并且从相应的单位电路依次从 第一阶段直到结束阶段。 在至少一个实施例中，每个单元电路接收（i）基于从显示面板驱动电路的外部接收的同步信号产生的时钟信号，（ii）基于同步信号产生的起始脉冲信号或信号 在与其自身的阶段不同的阶段中产生的线选择信号，以及（iii）清除信号。 在同步信号中包含异常的情况下，清除信号被激活，并且在随后的垂直扫描期间开始之前没有脉冲从移位寄存器输出。 这种配置实现了一种显示面板驱动电路，其防止显示无序或者抑制给予电源的负载增加，每个电源在同步信号中包括异常的情况下发生。

公开(公告)号：US08519764B2

公开(公告)日：2013-08-27

申请号：US13501198

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Kei Ikuta

IPC分类号： H03K3/00

CPC分类号： G11C19/28 ,  G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

摘要翻译： 构成移位寄存器的各级包括用于增加基于第一时钟（CKA）的扫描信号的电位的输出控制薄膜晶体管，用于增加连接到栅极的第一节点的电位的两个薄膜晶体管 基于从前级/后级输出的扫描信号的输出控制薄膜晶体管的端子和用于降低第一节点的电位的两个薄膜晶体管，基于从 在有关阶段之后的第三阶段。 移位寄存器基于四相时钟信号进行操作，包括提供给奇数级的两相时钟信号和提供给偶数级的两相时钟信号，其中相位偏移90度 彼此。