公开(公告)号：US20110001732A1

公开(公告)日：2011-01-06

申请号：US12735771

申请日：2008-10-22

申请人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane ,  Shinya Tanaka ,  Hajime Imai ,  Tetsuo Kikuchi

发明人： Hideki Morii ,  Akihisa Iwamoto ,  Takayuki Mizunaga ,  Yuuki Ohta ,  Masahiro Hirokane ,  Shinya Tanaka ,  Hajime Imai ,  Tetsuo Kikuchi

IPC分类号： G09G5/00 ,  G11C19/36

CPC分类号： G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： In at least one embodiment, each of stages connected in cascade includes a first circuit which causes a predetermined section in a corresponding one of the stages to be connected to a low-potential power source, the first circuit being constituted by TFTs, a first type of clock signal being used as a signal which is transferred to an output terminal of each of the stages so as to be outputted as an output signal, a second type of clock signal being used as a signal which drives the first circuit. With the arrangement, it is possible to realize a shift register circuit that is capable of further suppressing a shift phenomenon of a threshold voltage in each of the TFTs.

摘要翻译： 在至少一个实施例中，级联连接的每个级包括第一电路，其使相应级中的预定部分连接到低电位电源，第一电路由TFT构成，第一类型 时钟信号被用作被传送到每个级的输出端的信号，以作为输出信号输出，第二类型的时钟信号用作驱动第一电路的信号。 通过该结构，可以实现能够进一步抑制各TFT的阈值电压的偏移现象的移位寄存器电路。

公开(公告)号：US20120200544A1

公开(公告)日：2012-08-09

申请号：US13501215

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

IPC分类号： G06F3/038 ,  G11C19/28

CPC分类号： G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： In a shift register that operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock appears as a potential of a scanning signal, when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

摘要翻译： 在基于四相时钟信号工作的移位寄存器中，包括提供给奇数级的两相时钟信号和提供给偶数级的两相时钟信号，其中相位偏移90 在第一节点的电位处于高电平时，第一时钟的电位在扫描信号的电位下显现。 在这种配置中，基于从前级输出的扫描信号的脉冲将每级中包括的第一节点的电位设置为高电平，并且基于扫描信号的脉冲将其设置为低电平 在有关阶段后从第三阶段输出。

公开(公告)号：US08531224B2

公开(公告)日：2013-09-10

申请号：US13501215

申请日：2010-07-15

申请人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

发明人： Akihisa Iwamoto ,  Hideki Morii ,  Takayuki Mizunaga ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Takaharu Yamada ,  Satoshi Horiuchi ,  Chikao Yamasaki ,  Kei Ikuta

IPC分类号： H03K3/00

CPC分类号： G09G3/3685 ,  G09G2310/0275 ,  G09G2310/0286 ,  G11C19/287

摘要： An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver.In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

摘要翻译： 目的是在单片门驱动器内的移位寄存器中抑制时钟下降周期，同时抑制电路面积的增加，电流消耗的增加和成本增加，而不产生异常操作。 在基于提供给奇数级的两相时钟信号（GCK1，GCK3）和提供给奇数级的两相时钟信号（GCK2，GCK4）的四相时钟信号的移位寄存器（410）中， 到相位相互偏移90度的偶数级，当第一节点的电位处于高电平时，第一时钟（CKA）的电位作为扫描信号（GOUT）的电位出现 水平，在每个阶段。 在这种配置中，基于从前级输出的扫描信号的脉冲将每级中包括的第一节点的电位设置为高电平，并且基于扫描信号的脉冲将其设置为低电平 在有关阶段后从第三阶段输出。

公开(公告)号：US20130092927A1

公开(公告)日：2013-04-18

申请号：US13639138

申请日：2011-01-17

申请人： Atsuhito Murai ,  Shinya Tanaka ,  Hideki Kitagawa ,  Hajime Imai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

发明人： Atsuhito Murai ,  Shinya Tanaka ,  Hideki Kitagawa ,  Hajime Imai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

IPC分类号： H01L27/15

CPC分类号： H01L27/15 ,  G02F1/13318 ,  G02F1/13338 ,  G02F1/136204 ,  G02F1/1368 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/42384 ,  H01L29/78633 ,  H01L29/7869

摘要： The circuit board (1) of the present invention includes a plurality of transistor elements provided on a single insulating substrate (2) for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT (10) having a channel layer (11) formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT (20) having a channel layer (21) formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT (10) and the a-Si TFT (20) is a bottom-gate transistor.

摘要翻译： 本发明的电路板（1）包括设置在单个绝缘基板（2）上的多个晶体管元件，用于各个像素的二维排列或者在一组预定数量的像素中的各个像素。 多个晶体管元件中的至少一个是具有由氧化物半导体形成的沟道层（11）的氧化物TFT（10），并且多个晶体管元件中的至少另一个是具有 沟道层（21）由例如非晶硅半导体形成。 氧化物TFT（10）和a-Si TFT（20）中的每一个都是底栅晶体管。

公开(公告)号：US20110012880A1

公开(公告)日：2011-01-20

申请号：US12736222

申请日：2009-01-27

申请人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Hajime Imai ,  Hideki Kitagawa ,  Yoshiharu Kataoka

发明人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Hajime Imai ,  Hideki Kitagawa ,  Yoshiharu Kataoka

IPC分类号： G06F3/038 ,  H01L29/94 ,  H01L21/326 ,  G11C19/00

CPC分类号： H01L27/12 ,  G09G3/3677 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/13 ,  H01L28/86

摘要： In at least one embodiment, a TFT includes: a first capacitor formed of a first capacitor electrode connected to a source electrode and a second capacitor electrode; a second capacitor formed of a third capacitor electrode and a fourth capacitor electrode; a first lead-out line; a second lead-out line connected to a gate electrode; a third lead-out line; a fourth lead-out line; a first interconnection; and a second interconnection. This realizes a TFT which can be easily saved from being a defective product even if leakage occurs in a capacitor connected to a TFT body section.

摘要翻译： 在至少一个实施例中，TFT包括：由连接到源电极和第二电容器电极的第一电容器电极形成的第一电容器; 由第三电容器电极和第四电容器电极形成的第二电容器; 第一个引出线; 连接到栅电极的第二引出线; 第三个引出线; 第四个引出线; 第一个互连; 和第二互连。 这实现了即使在连接到TFT主体部分的电容器中发生泄漏，也可以容易地将其从劣质产品中保存下来。

公开(公告)号：US08963152B2

公开(公告)日：2015-02-24

申请号：US12867510

申请日：2008-10-09

申请人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Hajime Imai ,  Hideki Kitagawa ,  Yoshiharu Kataoka

发明人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Hajime Imai ,  Hideki Kitagawa ,  Yoshiharu Kataoka

IPC分类号： H01L29/41 ,  H01L27/12 ,  G09G3/36

CPC分类号： H01L27/1214 ,  G02F2201/124 ,  G09G3/3648 ,  G09G2310/0297 ,  H01L27/124

摘要： A distance (d1) from an edge of a first region (R) at places (D) where branch electrodes (4b) extending, which branch off from an electrode line (4a) of a second source/drain electrode (4), start to overlap with a first region (R) to the electrode line (4a) is 5 μm or more. This realizes a TFT including a comb-shaped source/drain structure that enables easy repair of a source-drain leakage.

摘要翻译： 在从第二源极/漏极（4）的电极线（4a）延伸的分支电极（4b）延伸的位置（D）处的第一区域（R）的边缘的距离（d1）开始 与电极线（4a）的第一区域（R）重叠为5μm以上。 这实现了包括梳状源极/漏极结构的TFT，其能够容易地修复源极漏极泄漏。

公开(公告)号：US20130146866A1

公开(公告)日：2013-06-13

申请号：US13643652

申请日：2011-03-02

申请人： Hideki Kitagawa ,  Shinya Tanaka ,  Hajime Imai ,  Atsuhito Murai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

发明人： Hideki Kitagawa ,  Shinya Tanaka ,  Hajime Imai ,  Atsuhito Murai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

IPC分类号： H01L27/12

CPC分类号： H01L27/1251 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1446 ,  H01L27/14632 ,  H01L27/14678

摘要： A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.

摘要翻译： 电路板（1）在绝缘基板（2）上包括多个晶体管元件。 多个晶体管元件中的至少一个是氧化物TFT（10），其包括作为沟道层（11）的氧化物半导体。 多个晶体管元件中的至少一个是与作为电路元件的功能的氧化物TFT（10）不同的a-SiTFT（20）（i），（ii）包括作为沟道层（21）的无定形 硅半导体。 氧化物TFT（10）是顶栅晶体管，并且a-SiTFT（20）是底栅晶体管。 这提供：一种配置，其可以（a）增强配备有作为电路部件的各自功能不同的TFT的电路板的性能，（b）减小安装TFT所需的面积; 以及电路基板的制造方法。

公开(公告)号：US09111810B2

公开(公告)日：2015-08-18

申请号：US13643652

申请日：2011-03-02

申请人： Hideki Kitagawa ,  Shinya Tanaka ,  Hajime Imai ,  Atsuhito Murai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

发明人： Hideki Kitagawa ,  Shinya Tanaka ,  Hajime Imai ,  Atsuhito Murai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

IPC分类号： H01L29/10 ,  H01L29/12 ,  H01L27/12 ,  H01L27/146 ,  H01L27/144

CPC分类号： H01L27/1251 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1446 ,  H01L27/14632 ,  H01L27/14678

摘要： A circuit board (1) includes a plurality of transistor elements on an insulating substrate (2). At least one of the plurality of transistor elements is an oxide TFT (10) including, as a channel layer (11), an oxide semiconductor. At least one of the plurality of transistor elements is an a-SiTFT (20) (i) being different from the oxide TFT (10) in functions as circuit components and (ii) including, as a channel layer (21), an amorphous silicon semiconductor. The oxide TFT (10) is a top gate transistor, and the a-SiTFT (20) is a bottom gate transistor. This provides: a configuration that can (a) enhance the performance of the circuit board equipped with the TFTs differing in their respective functions as circuit components and (b) reduce the area necessary for mounting the TFTs; and a method for producing the circuit board.

摘要翻译： 电路板（1）在绝缘基板（2）上包括多个晶体管元件。 多个晶体管元件中的至少一个是氧化物TFT（10），其包括作为沟道层（11）的氧化物半导体。 多个晶体管元件中的至少一个是与作为电路元件的功能的氧化物TFT（10）不同的a-SiTFT（20）（i），（ii）包括作为沟道层（21）的无定形 硅半导体。 氧化物TFT（10）是顶栅晶体管，并且a-SiTFT（20）是底栅晶体管。 这提供：一种配置，其可以（a）增强配备有作为电路部件的各自功能不同的TFT的电路板的性能，（b）减小安装TFT所需的面积; 以及电路基板的制造方法。

公开(公告)号：US20130214279A1

公开(公告)日：2013-08-22

申请号：US13695082

申请日：2011-02-23

申请人： Jun Nishimura ,  Hideki Kitagawa ,  Atsuhito Murai ,  Hajime Imai ,  Shinya Tanaka ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Junya Shimada ,  Kazunori Morimoto

发明人： Jun Nishimura ,  Hideki Kitagawa ,  Atsuhito Murai ,  Hajime Imai ,  Shinya Tanaka ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Junya Shimada ,  Kazunori Morimoto

IPC分类号： H01L27/02

CPC分类号： H01L29/78663 ,  G02F1/13338 ,  G02F1/13624 ,  G06F3/0412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L29/78633 ,  H01L29/7869

摘要： A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.

摘要翻译： 氧化物TFT元件（3）的源极和漏极电极层（3s / 3d）由第一导电层形成。 氧化物TFT元件（3）的栅极（3g）和a-Si TFT元件（5）的栅电极（5g）由单个导电层即第二导电层形成。 a-Si TFT元件（5）的源极和漏极电极层（5s / 5d）由第三导电层形成。 第三导电层形成在第二导电层上方的厚度方向上，其中每个导电层堆叠在绝缘基板（2）上。 此外，第一导电层在厚度方向上形成在第二导电层的下方。 因此，可以提供可以使形成在绝缘基板上的晶体管元件的集成度提高的电路板。

公开(公告)号：US20110001736A1

公开(公告)日：2011-01-06

申请号：US12867510

申请日：2008-10-09

申请人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Hajime Imai ,  Hideki Kitagawa ,  Yoshiharu Kataoka

发明人： Shinya Tanaka ,  Tetsuo Kikuchi ,  Hajime Imai ,  Hideki Kitagawa ,  Yoshiharu Kataoka

IPC分类号： G09G5/00 ,  H01L29/786

CPC分类号： H01L27/1214 ,  G02F2201/124 ,  G09G3/3648 ,  G09G2310/0297 ,  H01L27/124

摘要： A distance (d1) from an edge of a first region (R) at places (D) where branch electrodes (4b) extending, which branch off from an electrode line (4a) of a second source/drain electrode (4), start to overlap with a first region (R) to the electrode line (4a) is 5 μm or more. This realizes a TFT including a comb-shaped source/drain structure that enables easy repair of a source-drain leakage.

摘要翻译： 在从第二源极/漏极（4）的电极线（4a）延伸的分支电极（4b）延伸的位置（D）处的第一区域（R）的边缘的距离（d1）开始 与电极线（4a）的第一区域（R）重叠为5μm以上。 这实现了包括梳状源极/漏极结构的TFT，其能够容易地修复源极漏极泄漏。