公开(公告)号：US20080317522A1

公开(公告)日：2008-12-25

申请号：US11766846

申请日：2007-06-22

申请人： Jeffrey Allen Ardery ,  Jason Kyle Romain ,  Jerry Wayne Smith ,  Fangsheng Wu

发明人： Jeffrey Allen Ardery ,  Jason Kyle Romain ,  Jerry Wayne Smith ,  Fangsheng Wu

IPC分类号： G03G15/20

CPC分类号： G03G15/2025 ,  G03G2215/2035

摘要： A fuser assembly includes a first end cap, and a second end cap spaced apart from the first end cap along an axis orthogonal to a sheet feed direction. A fuser belt is positioned between and supported by the first end cap and the second end cap to rotate around the axis in a belt moving direction at the nip corresponding to the sheet feed direction. A heater assembly is located in the hollow interior of the fuser belt. A plurality of ribs is positioned to contact the interior surface of the fuser belt. A first rib is connected to one of the first end cap and the heater assembly. A second rib is connected to one of the second end cap and the heater assembly. Each of the plurality of ribs is oriented to longitudinally extend at an acute angle with respect to the belt moving direction.

摘要翻译： 定影器组件包括第一端盖和沿着与片材进给方向正交的轴线与第一端盖间隔开的第二端盖。 定影带定位在第一端盖之间并由第一端盖支撑，并且第二端盖在与片材进给方向对应的辊隙处沿带移动方向围绕轴线旋转。 加热器组件位于定影带的中空内部。 定位多个肋以接触定影带的内表面。 第一肋连接到第一端盖和加热器组件中的一个。 第二肋连接到第二端盖和加热器组件中的一个。 多个肋中的每一个被定向成相对于带移动方向以锐角纵向延伸。

公开(公告)号：US20080288753A1

公开(公告)日：2008-11-20

申请号：US12183086

申请日：2008-07-31

申请人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30101 ,  G06F9/322 ,  G06F9/3806

摘要： An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode information which describes the instruction address as being related to an implicit subroutine call to a subroutine. In response to the predecode information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction.

公开(公告)号：US20080250229A1

公开(公告)日：2008-10-09

申请号：US11696508

申请日：2007-04-04

申请人： Brian Michael Stempel ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Brian Michael Stempel ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/30

CPC分类号： G06F9/30047 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/382

摘要： In a processor executing instructions from a variable-length instruction set, a preload instruction is operative to retrieve from memory a data block corresponding to an instruction cache line, pre-decode instructions from a variable-length instruction set in the data block, and load the instructions and pre-decode information into the instruction cache. An instruction execution unit indicates to a pre-decoder the position within the data block of a first valid instruction. The pre-decoder successively determines the length of each instruction and hence the instruction boundaries. An instruction cache line offset indicator that identifies the position of the first valid instruction may be generated and provided to the pre-decoder in a variety of ways.

摘要翻译： 在执行来自可变长度指令集的指令的处理器中，预加载指令用于从存储器检索与指令高速缓存行相对应的数据块，对来自数据块中的可变长度指令集的指令进行预解码，以及负载 指令和预解码信息到指令缓存中。 指令执行单元向预解码器指示第一有效指令的数据块内的位置。 预解码器依次确定每个指令的长度，从而确定指令边界。 可以以各种方式生成识别第一有效指令的位置的指令高速缓存行偏移指示符并将其提供给预解码器。

公开(公告)号：US07421568B2

公开(公告)日：2008-09-02

申请号：US11073284

申请日：2005-03-04

申请人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

发明人： Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Rodney Wayne Smith ,  Thomas Andrew Sartorius

IPC分类号： G06F9/30

CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3816 ,  G06F12/0875 ,  Y02D10/13

摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.

摘要翻译： 描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。 处理器以多种模式运行。 其中一种模式限制了可以获取并执行到较长长度指令的指令。 指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。 处理器操作模式状态信息指示处理器的程序指定的操作模式。 处理器从指令缓存器中获取指令以执行。 作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取 取。

公开(公告)号：US20080177987A1

公开(公告)日：2008-07-24

申请号：US11626424

申请日：2007-01-24

申请人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Nathan Samuel Nunamaker ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Nathan Samuel Nunamaker ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/312

CPC分类号： G06F9/3017 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Intermediate results are passed between constituent instructions of an expanded instruction using register renaming resources and control logic. A first constituent instruction generates intermediate results and is assigned a PRN in a constituent instruction rename table, and writes intermediate results to the identified physical register. A second constituent instruction performs a look up in the constituent instruction rename table and reads the intermediate results from the physical register. Constituent instruction rename logic tracks the constituent instructions through the pipeline, and delete the constituent instruction rename table entry and returns the PRN to a free list when the second constituent instruction has read the intermediate results.

摘要翻译： 使用寄存器重命名资源和控制逻辑在扩展指令的组成指令之间传递中间结果。 第一组成指令生成中间结果，并在组成指令重命名表中分配PRN，并将中间结果写入所识别的物理寄存器。 第二个构成指令在组成指令重命名表中执行查询，并从物理寄存器读取中间结果。 组分指令重命名逻辑通过流水线跟踪组成指令，并删除组成指令重命名表项，并在第二组成指令读取中间结果时将PRN返回到空闲列表。

公开(公告)号：US20080124110A1

公开(公告)日：2008-05-29

申请号：US11564413

申请日：2006-11-29

申请人： Douglas Campbell Hamilton ,  Jerry Wayne Smith

发明人： Douglas Campbell Hamilton ,  Jerry Wayne Smith

IPC分类号： G03G15/20

CPC分类号： G03G15/2039

摘要： The present disclosure relates to a system including a component and a heating device. The component may include a compressible layer composed of elastomeric material having a thermal conductivity of ≦0.4 W m−1K−1. A processor in communication with the heating device, may he configured to select the heating device temperature based upon a previous temperature of the heating device to establish the temperature of the component. Optionally, the component may be maintained at a temperature of about or below 150° C.

摘要翻译： 本公开涉及一种包括部件和加热装置的系统。 该组件可以包括由弹性体材料构成的可压缩层，该可弹性材料具有<= 0.4W M -1 -K -1的热导率。 与加热装置通信的处理器可以被配置为基于加热装置的先前温度来选择加热装置温度以建立部件的温度。 任选地，组分可以保持在约或低于150℃的温度

公开(公告)号：US07365286B2

公开(公告)日：2008-04-29

申请号：US11421785

申请日：2006-06-02

申请人： Gregory Daniel Creteau ,  Jerry Wayne Smith

发明人： Gregory Daniel Creteau ,  Jerry Wayne Smith

IPC分类号： G03G15/20 ,  H05B3/06 ,  H05B3/08

CPC分类号： H05B3/0095

摘要： A heater assembly includes a heater housing with strain relief features for wires associated with electronic components, such as a thermistor and/or thermal cut-off (TCO) device, coupled to a heating element. The heater assembly may be used in a fixing device or fuser in an image forming apparatus including, but not limited to, printers, copiers, faxes, multifunctional devices or all-in-one devices.

摘要翻译： 加热器组件包括加热器壳体，其具有用于与电子部件相关联的线的应变消除特征，诸如耦合到加热元件的热​​敏电阻和/或热切断（TCO）装置。 加热器组件可以用在图像形成设备中的定影设备或定影器中，该设备包括但不限于打印机，复印机，传真机，多功能设备或一体机设备。

公开(公告)号：US20080040587A1

公开(公告)日：2008-02-14

申请号：US11463379

申请日：2006-08-09

申请人： Kevin Charles Burke ,  Brian Michael Stempel ,  Daren Streett ,  Kevin Allen Sapp ,  Leslie Mark DeBruyne ,  Nabil Amir Rizk ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Kevin Charles Burke ,  Brian Michael Stempel ,  Daren Streett ,  Kevin Allen Sapp ,  Leslie Mark DeBruyne ,  Nabil Amir Rizk ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F9/44

CPC分类号： G06F11/3648

摘要： A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.

摘要翻译： 处理器可操作以执行两个或更多个指令集，每个指令集处于不同的指令集操作模式。 当执行每条指令时，调试电路将当前指令集操作模式与编程器发送的目标指令集操作模式进行比较，并输出其中的警报或指示。 警报或指示还可以依赖于在预定目标地址范围内的指令地址。 警报或指示可以包括停止执行的断点信号和/或作为处理器的外部信号输出的断点信号。 可以另外输出处理器在指令集操作模式中检测到匹配的指令地址。 附加地或替代地，警报或指示可以包括启动或停止跟踪操作，引起异常或任何其他已知的调试器功能。

公开(公告)号：US20080034187A1

公开(公告)日：2008-02-07

申请号：US11461883

申请日：2006-08-02

申请人： Brian Michael Stempel ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

发明人： Brian Michael Stempel ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith

IPC分类号： G06F12/00

CPC分类号： G06F9/3804 ,  G06F9/3806

摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.

摘要翻译： 处理器对非顺序指令地址执行预取操作。 如果第一指令地址在指令高速缓存中丢失并且作为获取操作的一部分访问高阶存储器，并且检测并预测与第一指令地址或第一指令地址之后的地址相关联的分支指令，则预取 在高级存储器访问期间使用预测的分支目标地址执行操作。 如果预取分支目标地址在预取操作期间在指令高速缓存中命中，则不检索相关联的指令以节省功率。 如果在预取操作期间预测的分支目标地址在指令高速缓存中丢失，则可以使用预测的分支指令地址来启动高阶存储器访问。 在任一种情况下，第一指令地址被重新加载到提取级流水线中以等待指令从其高阶存储器访问返回。

公开(公告)号：US07310933B2

公开(公告)日：2007-12-25

申请号：US11545983

申请日：2006-10-10

申请人： Geoffrey D. Hietpas ,  Steven Wayne Smith

发明人： Geoffrey D. Hietpas ,  Steven Wayne Smith

IPC分类号： D02G3/02 ,  D03D15/00

CPC分类号： D01F8/14 ,  D01D5/253 ,  Y10T428/2904 ,  Y10T428/2913 ,  Y10T428/2915 ,  Y10T428/2924 ,  Y10T428/2929 ,  Y10T428/2931 ,  Y10T442/30 ,  Y10T442/3065 ,  Y10T442/425 ,  Y10T442/60

摘要： The invention provides a bicomponent staple fiber comprising poly(ethylene terephthalate) and poly(trimethylene terephthalate) wherein the bicomponent fiber has a substantially oval cross-section shape having an aspect ratio A:B of about 2:1 to about 5:1 wherein A is a fiber cross-section major axis length and B is a fiber cross-section minor axis length, a polymer interface substantially perpendicular to the major axis, a cross-section configuration selected from the group consisting of side-by-side and eccentric sheath-core, a tenacity at 10% elongation of about 1.1 cN/dtex to about 3.5 cN/dtex, a free-fiber length retention of about 40% to about 85%, and a tow crimp development value of about 30 to 55%, and a spun yarn comprising the bicomponent staple fiber.