公开(公告)号：US08216890B2

公开(公告)日：2012-07-10

申请号：US12550658

申请日：2009-08-31

申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L21/336

CPC分类号： H01L29/93 ,  H01L29/7391

摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.

摘要翻译： 变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。 具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。 在第二掺杂半导体区域和第二电极之间形成超破坏结。 栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。 还提供了变容二极管的设计结构。

公开(公告)号：US08012814B2

公开(公告)日：2011-09-06

申请号：US12188366

申请日：2008-08-08

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1203 ,  H01L27/1207

摘要： A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.

摘要翻译： 保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。 形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。 暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

公开(公告)号：US08008142B2

公开(公告)日：2011-08-30

申请号：US12538213

申请日：2009-08-10

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Alan D. Norris ,  Robert M. Rassel ,  Yun Shi

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Alan D. Norris ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L21/338

CPC分类号： H01L29/7839 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66659

摘要： A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.

摘要翻译： 肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。 肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构 另一侧的掺杂保护环。 肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。 掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。 肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。 还提供了用于本发明的肖特基势垒二极管的设计结构。

公开(公告)号：US20110161896A1

公开(公告)日：2011-06-30

申请号：US13042947

申请日：2011-03-08

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

IPC分类号： G06F17/50

CPC分类号： H01L27/115 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.

摘要翻译： 在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。 横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。 在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。 横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

公开(公告)号：US07939911B2

公开(公告)日：2011-05-10

申请号：US12191683

申请日：2008-08-14

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

IPC分类号： H01L29/00

CPC分类号： H01L27/115 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.

摘要翻译： 在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。 横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。 在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。 横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

公开(公告)号：US07790543B2

公开(公告)日：2010-09-07

申请号：US11972941

申请日：2008-01-11

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

IPC分类号： H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

摘要： Device structures for a metal-oxide-semiconductor field effect transistor (MOSFET) that is suitable for operation at relatively high voltages and methods of forming same. The MOSFET, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a channel in a semiconductor body that is self-aligned with a gate electrode. The gate electrode and semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are separated by a gap that is filled by a gate dielectric layer. The gate dielectric layer may be composed of thermal oxide layers grown on adjacent sidewalls of the semiconductor body and gate electrode, in combination with an optional deposited dielectric material that fills the remaining gap between the thermal oxide layers.

摘要翻译： 适用于在较高电压下工作的金属氧化物半导体场效应晶体管（MOSFET）的器件结构及其形成方法。 使用绝缘体上半导体（SOI）衬底形成的MOSFET包括半导体本体中与栅电极自对准的沟道。 由SOI衬底的单晶SOI层形成的栅电极和半导体本体由被栅极电介质层填充的间隙分开。 栅极电介质层可以由在半导体主体和栅电极的相邻侧壁上生长的热氧化物层组合，并与填充热氧化物层之间的剩余间隙的任选沉积的电介质材料组合。

公开(公告)号：US07790524B2

公开(公告)日：2010-09-07

申请号：US11972949

申请日：2008-01-11

申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, Jr. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

IPC分类号： H01L21/00

CPC分类号： H01L29/7881 ,  H01L29/66825

摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode separated from the semiconductor body by the floating gate electrode. The floating gate electrode, the control gate electrode, and the semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are respectively separated by dielectric layers. The dielectric layers may each be composed of thermal oxide layers grown on confronting sidewalls of the semiconductor body, the floating gate electrode, and the control gate electrode. An optional deposited dielectric material may fill any remaining gap between either pair of the thermal oxide layers.

摘要翻译： 用于非易失性随机存取存储器（NVRAM）中的存储器单元的装置和设计结构以及使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法。 使用绝缘体上半导体（SOI）衬底形成的器件结构包括通过浮栅电极与半导体本体分离的浮栅电极，半导体本体和控制栅电极。 由SOI衬底的单晶SOI层形成的浮置栅电极，控制栅电极和半导体本体分别由电介质层分离。 介电层可以各自由在半导体本体，浮栅电极和控制栅电极的相对侧壁上生长的热氧化物层组成。 任选沉积的介电材料可以填充任何一对热氧化物层之间的剩余间隙。

公开(公告)号：US20100032761A1

公开(公告)日：2010-02-11

申请号：US12188381

申请日：2008-08-08

申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

IPC分类号： H01L27/12

CPC分类号： H01L27/088 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1207

摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

摘要翻译： 第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。 第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。 第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。 还提供了用于半导体结构的设计结构。

公开(公告)号：US20090302355A1

公开(公告)日：2009-12-10

申请号：US12132638

申请日：2008-06-04

申请人： John J. Pekarik ,  Richard A. Phelps ,  Robert M. Rassel ,  Yun Shi

发明人： John J. Pekarik ,  Richard A. Phelps ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L29/808 ,  H01L21/337 ,  G06F17/50

CPC分类号： H01L29/8086 ,  H01L29/66901

摘要： A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer.

摘要翻译： 更具体地，涉及用于制造SOI中的JFET的设计结构，JFET和制造JFET的方法。 JFET包括直接在SOI层上形成的栅极多晶硅，并且栅极氧化层插入在栅极多晶硅和SOI层的外边缘之间。

公开(公告)号：US20090250772A1

公开(公告)日：2009-10-08

申请号：US12099175

申请日：2008-04-08

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Stephen E. Luce ,  John J. Pekarik ,  Yun Shi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/423 ,  H01L29/66575

摘要： A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

摘要翻译： 提供一种半导体结构和制造方法，更具体地说，具有身体接触的场效应晶体管及其制造方法。 该结构包括具有第一导电类型的凸起源极区域和延伸到器件主体的凸起源极区域下方的有源区域的器件。 有源区具有不同于第一导电类型的第二导电类型。 接触区域与有源区域电接触。 该方法包括在器件的有源区上形成凸起的源极区域，并形成与有源区域相同的导电类型的接触区域，其中有源区域在接触区域和器件的主体之间形成接触体。