公开(公告)号：US11188330B2

公开(公告)日：2021-11-30

申请号：US16324239

申请日：2017-08-14

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt ,  François Christopher Jacques Botman

IPC: G06F9/30 ,  G06F15/80 ,  G06F7/544 ,  G06F17/16

Abstract: An apparatus comprises processing circuitry, a number of vector register and a number of scalar registers. An instruction decoder is provided which supports decoding of a vector multiply-add instruction specifying at least one vector register and at least one scalar register. In response to the vector multiply-add instruction, the decoder controls the processing circuitry to perform a vector multiply-add instruction in which each lane of processing generates a respective result data element corresponding to a sum of difference of a product value and an addend value, with the product value comprising the product of a respective data element of a first vector value and a multiplier value. In each lane of processing at least one of the multiplier value and the addend value is specified as a portion of a scalar value stored in a scalar register.

公开(公告)号：US10768934B2

公开(公告)日：2020-09-08

申请号：US16081464

申请日：2017-03-21

Applicant: ARM Limited

Inventor： Thomas Christopher Grocutt

IPC: G06F9/30 ,  G06F9/38 ,  G06F8/41

Abstract: A data processing system supports a predicated-loop instruction that controls vectorised execution of a program loop body in respect of a plurality of vector elements. When the number of elements to be processed is not a whole number multiple of the number of lanes of processing supported for that element size, then the predicated-loop instruction controls suppression of processing in one or more lanes not required.

公开(公告)号：US10599428B2

公开(公告)日：2020-03-24

申请号：US15078149

申请日：2016-03-23

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt

IPC: G06F9/30 ,  G06F15/82 ,  G06F9/38 ,  G06F15/80 ,  G06F9/32

Abstract: Processing circuitry supports overlapped execution of vector instructions when at least one beat of a first vector instruction is performed in parallel with at least one beat of a second vector instruction. The processing circuitry also supports mixed-scalar-vector instructions for which one of a destination register and one or more source registers is a vector register and another is a scalar register. In a sequence including first and subsequent mixed-scalar-vector instructions, instances of relaxed execution which can potentially lead to uncertain and incorrect results are permitted by the processing circuitry when the instructions are separated by fewer than a predetermined number of intervening instructions. In practice the situations which lead to the uncertain results are very rare and so it is not justified providing relatively expensive dependency checking circuitry for eliminating such cases.

公开(公告)号：US10162633B2

公开(公告)日：2018-12-25

申请号：US15494911

申请日：2017-04-24

Applicant: ARM LIMITED

Inventor： François Christopher Jacques Botman ,  Thomas Christopher Grocutt

IPC: G06F9/30

Abstract: An apparatus has processing circuitry comprising multiplier circuitry for performing multiplication on a pair of input operands. In response to a shift instruction specifying at least one shift amount and a source operand comprising at least one data element, the source operand and a shift operand determined in dependence on the shift amount are provided as input operands to the multiplier circuitry and the multiplier circuitry is controlled to perform at least one multiplication which is equivalent to shifting a corresponding data element of the source operand by a number of bits specified by a corresponding shift amount to generate a shift result value.

公开(公告)号：US09501667B2

公开(公告)日：2016-11-22

申请号：US14310332

申请日：2014-06-20

Applicant: ARM Limited

Inventor： Simon John Craske ,  Thomas Christopher Grocutt

IPC: G06F9/38 ,  G06F7/04 ,  G06F17/30 ,  H04N7/16 ,  G06F21/79 ,  G06F21/55

CPC classification number: G06F21/79 ,  G06F9/3806 ,  G06F21/554 ,  G06F2221/2141 ,  G06F2221/2149

Abstract: A data processing apparatus supports operation in both a secure domain and a less secure domain. The secure domain has access to data that is not accessible when operating the less secure domain. Prediction circuitry generates a domain prediction indicating whether a given processing action (such as a memory access) is to be performed in association with the secure domain or with the less secure domain. In this way, an appropriate set of memory permission data for controlling access by different privilege levels in the domains may be selected and applied by an appropriate memory protection unit. If the domain prediction is incorrect, then the processing is stalled and the given processing action retried.

Abstract translation: 数据处理装置支持安全域和较不安全域中的操作。 安全域可以访问在操作较不安全的域时无法访问的数据。 预测电路产生一个域预测，指示一个给定的处理动作（例如存储器访问）是否与安全域相关联地执行，或者与较不安全的域相关联地执行。 以这种方式，可以由适当的存储器保护单元选择适当的用于控制域中不同特权级别的访问的存储器许可数据集合。 如果域预测不正确，则停止处理并重试给定的处理动作。

公开(公告)号：US09116711B2

公开(公告)日：2015-08-25

申请号：US13680298

申请日：2012-11-19

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt

IPC: G06F21/00 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F21/52 ,  G06F12/14 ,  G06F9/30 ,  G06F21/74

CPC classification number: G06F9/3861 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/461 ,  G06F9/4812 ,  G06F12/1491 ,  G06F21/52 ,  G06F21/74 ,  G06F2209/481 ,  G06F2221/034

Abstract: Processing circuitry can operate in a secure domain and a less secure domain. In response to an initial exception from background processing performed by the processing circuitry, state saving of data from a first subset of registers is performed by exception control circuitry before triggering an exception handling routine, while the exception handling routine has responsibility for performing state saving of data from a second subset of registers. In response to a first exception causing a transition from the secure domain from a less secure domain, where the background processing was in the less secure domain, the exception control circuitry performs additional state saving of data from the second set of registers before triggering the exception handling routine. In response to a tail-chained exception causing a transition from the secure domain to the less secure domain, the exception handling routine is triggered without performing an additional state saving.

Abstract translation: 处理电路可以在安全域和较不安全的域中操作。 响应于由处理电路执行的后台处理的初始异常，在触发异常处理例程之前由异常控制电路执行来自寄存器的第一子集的数据的状态保存，而异常处理例程有责任执行状态保存 数据来自第二个寄存器子集。 响应于第一个异常导致来自不安全域的安全域的转移，其中后台处理在较不安全的域中，异常控制电路在触发异常之前执行来自第二组寄存器的附加状态保存数据 处理程序。 为了响应引起从安全域到不太安全域的过渡的尾部链接异常，在不执行附加状态保存的情况下触发异常处理例程。

公开(公告)号：US12248562B2

公开(公告)日：2025-03-11

申请号：US17756949

申请日：2020-11-11

Applicant: Arm Limited

Inventor： Thomas Christopher Grocutt

IPC: G06F21/54 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F21/55

Abstract: A processing circuitry having a secure domain and a less secure domain. A control storage location stores a domain transition disable configuration parameter specifying whether domain transitions between the secure domain and the less secure domain are enabled or disabled in at least one mode of the process-ing circuitry. In the at least one mode of the processing circuitry, when the domain transition disable configuration parameter specifies that said domain transitions are disabled in said at least one mode, a disabled domain transition fault is signalled in response to an attempt to transition between domains in either direction. This can help support lazy configuration of resources for the secure domain or less secure domain for a thread expected only to need the other domain.

公开(公告)号：US20240411935A1

公开(公告)日：2024-12-12

申请号：US18700886

申请日：2022-09-14

Applicant: Arm Limited

Inventor： François Christopher Jacques Botman ,  Thomas Christopher Grocutt

IPC: G06F21/64

Abstract: An apparatus and method are described for handling sealed capabilities. The apparatus has processing circuitry to perform processing operations during which access requests to memory are generated, wherein the processing circuitry is arranged to generate memory addresses for the access requests using capabilities that identify constraining information. Checking circuitry then determines whether a given access request whose memory address is generated using a given capability is permitted based on the constraining information identified by that given capability, and based on a level of trust associated with the given access request. Each capability has a capability level of trust associated therewith, and the level of trust associated with the given access request is dependent on both a current mode level of trust associated with a current mode of operation of the processing circuitry, and the capability level of trust of the given capability. At least one of the capabilities is settable as a sealed capability, and the apparatus further comprises sealed capability handling circuitry to prevent the processing circuitry performing at least one processing operation using a given sealed capability when the current mode level of trust is a lower level of trust than the capability level of trust of the given sealed capability.

公开(公告)号：US11474956B2

公开(公告)日：2022-10-18

申请号：US17260026

申请日：2019-06-06

Applicant: Arm Limited

Inventor： Thomas Christopher Grocutt

IPC: G06F12/14 ,  G06F3/06

Abstract: An apparatus comprises processing circuitry to issue memory access requests specifying a target address identifying a location to be accessed in a memory system; and a memory protection unit (MRU) comprising permission checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a memory protection table stored in the memory system. The memory protection table comprises memory protection entries each specifying access permissions for a corresponding address region of variable size within an address space, where the variable size can be a number of bytes other than a power of 2.

公开(公告)号：US11354404B2

公开(公告)日：2022-06-07

申请号：US17266855

申请日：2019-08-22

Applicant: Arm Limited

Inventor： Thomas Christopher Grocutt

IPC: G06F21/54 ,  G06F9/30 ,  G06F9/38 ,  G06F21/55 ,  G06F21/64 ,  G06F21/74

Abstract: An apparatus has processing circuitry 4 supporting a number of security domains, and within each domain supporting a number of modes including a handler mode for exception processing and a thread mode for background processing. For an exception entry transition from secure thread mode to secure handler mode, a transition disable indicator 42 is set. For at least one type of exception return transition to processing in the secure domain and the thread mode when the transition disable indicator 42 is set, a fault is signaled. This can protect against some security attacks.