公开(公告)号：US20240296132A1

公开(公告)日：2024-09-05

申请号：US18574277

申请日：2022-06-21

Applicant: Arm Limited

Inventor： Mbou Eyole ,  Giacomo Gabrielli ,  Balaji Venu

IPC: G06F13/16 ,  G06F13/26

CPC classification number: G06F13/1673 ,  G06F13/161 ,  G06F13/26

Abstract: There is provided a data processing apparatus and method. The data processing apparatus comprises a plurality of processing elements connected via a network arranged on a single chip to form a spatial architecture. Each processing element comprising processing circuitry to perform processing operations and memory control circuitry to perform data transfer operations and to issue data transfer requests for requested data to the network. The memory control circuitry is configured to monitor the network to retrieve the requested data from the network. Each processing element is further provided with local storage circuitry comprising a plurality of local storage sectors to store data associated with the processing operations, and auxiliary memory control circuitry to monitor the network to detect stalled data (S60). The auxiliary memory control circuitry is configured to transfer the stalled data from the network to an auxiliary storage buffer (S66) dynamically selected from amongst the plurality of local storage sectors (S64).

公开(公告)号：US12045622B2

公开(公告)日：2024-07-23

申请号：US17941404

申请日：2022-09-09

Applicant: Arm Limited

Inventor： Matthew James Walker ,  Mbou Eyole ,  Giacomo Gabrielli ,  Balaji Venu

IPC: G06F9/38

CPC classification number: G06F9/3856 ,  G06F9/3802

Abstract: One or more triggered-instruction processing elements are provided, a given triggered-instruction processing element comprising execution circuitry to execute processing operations in response to instructions according to a triggered instruction architecture. Input channel processing circuitry receives a given tagged data item (comprising a data value and a tag value) for a given input channel, and in response controls enqueuing of the data value of the given tagged data item to a selected buffer structure selected from among at least two buffer structures mapped onto register storage accessible to one or more of the triggered-instruction processing elements in response to a computation instruction for controlling performance of a computation operation. The selected buffer structure is selected based at least on the tag value, so data values of tagged data items specifying different tag values for the given input channel are allocatable to different buffer structures.

公开(公告)号：US11176012B2

公开(公告)日：2021-11-16

申请号：US16823180

申请日：2020-03-18

Applicant: Arm Limited

Inventor： Emre Ozer ,  Xabier Iturbe ,  Balaji Venu

IPC: G06F11/00 ,  G06F11/27 ,  G06F11/22 ,  G06F11/16

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.

公开(公告)号：US11022649B2

公开(公告)日：2021-06-01

申请号：US16512911

申请日：2019-07-16

Applicant: Arm Limited

Inventor： Balaji Venu ,  Reiley Jeyapaul

IPC: G06F30/367 ,  G06F30/33 ,  G06F30/30 ,  G01R31/00 ,  G01R31/317 ,  G06F11/00

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for at least one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

公开(公告)号：US10817369B2

公开(公告)日：2020-10-27

申请号：US16225523

申请日：2018-12-19

Applicant: ARM Limited

Inventor： Reiley Jeyapaul ,  Balaji Venu ,  Xabier Iturbe ,  Emre Özer ,  Antony John Penton

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

公开(公告)号：US10747601B2

公开(公告)日：2020-08-18

申请号：US16206189

申请日：2018-11-30

Applicant: Arm Limited

Inventor： Reiley Jeyapaul ,  Balaji Venu

IPC: G06F17/50 ,  G06F11/00 ,  G06F30/30 ,  G06F30/33 ,  G06F30/367

Abstract: An apparatus is provided to measure vulnerability of a circuit to transient errors. The circuit includes processing circuitry and a plurality of flops. The apparatus includes categorisation obtaining circuitry that obtains a vulnerability categorisation of the flops. The vulnerability categorisation indicates whether each flop is vulnerable, conditionally vulnerable, or isolated. Analysis circuitry determines, for one cycle of the processing circuitry, a set of the flops that are currently vulnerable, based on the vulnerability categorisation of the flops.

公开(公告)号：US10289332B2

公开(公告)日：2019-05-14

申请号：US15493609

申请日：2017-04-21

Applicant: ARM Limited

Inventor： Xabier Iturbe ,  Emre Özer ,  Balaji Venu ,  Antony John Penton

IPC: G06F3/06 ,  G06F11/10

Abstract: An apparatus and method are provided for increasing resilience to faults. The apparatus comprises processing circuitry for executing a plurality of code sequences including at least one critical code sequence, and configuration storage for storing mode control data for the processing circuitry. When the processing circuitry is executing a critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry, where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry. By increasing the resilience to faults, this reduces the chance that any such fault will manifest itself as an error in the processing operations being performed by the apparatus.