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公开(公告)号：US20190188896A1
公开(公告)日：2019-06-20
申请号：US16218982
申请日：2018-12-13
Applicant: Arm Limited
Inventor： Frode Heggelund , Toni Viki Brkic , Christian Vik Grovdal , Lars Oskar Flordal
Abstract: A graphics processing system can divide a render output into plural larger patches, with each larger patch encompassing plural smaller patches. A rasteriser of the system tests a larger patch against a primitive to be processed to determine if the primitive covers the larger patch. When it is determined that the primitive only partially covers the larger patch, the larger patch is sub-divided into plural smaller patches and at least one of the smaller patches is re-tested against the primitive. Conversely, when it is determined that the primitive completely covers the larger patch, the larger patch is output from the rasteriser in respect of the primitive for processing by a subsequent stage, of the graphics processing system. The system can provide efficient, hierarchal, processing of primitives, whilst helping to prevent the output of the rasteriser from becoming blocked.
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公开(公告)号：US10311016B2
公开(公告)日：2019-06-04
申请号：US15607919
申请日：2017-05-30
Applicant: ARM Limited
Inventor： Frode Heggelund , Toni Viki Brkic , Reimar Gisbert Döffinger
Abstract: A graphics processing pipeline includes a rasteriser, an early culling tester, a renderer, a late culling tester, and a culling test data buffer that stores data values for use by the early and late culling testers. The testing of fragments by the early and late culling testers is controlled in accordance with a first set of state information indicative of when a culling test operation to be used to determine whether to cull the fragments is to be performed, and a second set of state information indicative of when to determine whether to update the culling test data buffer with data for the fragments based on a culling test operation, allocated to the fragments.
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公开(公告)号：US20180300915A1
公开(公告)日：2018-10-18
申请号：US15934223
申请日：2018-03-23
Applicant: Arm Limited
Inventor： Frode Heggelund
Abstract: When performing conservative rasterisation in a graphics processing pipeline, modified edge information that accounts for an error in the dimensions of a primitive is determined by a primitive set-up stage. That modified edge information is then used by a rasterisation stage to determine whether the primitive covers one or more sampling points associated with pixels to be displayed. The same modified edge information can also be used to determine if the pixels are fully covered by the primitive irrespective of any rounding effects (errors) in the position of the (vertices of the) primitive.
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公开(公告)号：US09805447B2
公开(公告)日：2017-10-31
申请号：US13690142
申请日：2012-11-30
Applicant: ARM Limited
Inventor： Andreas Engh-halstvedt , Jorn Nystad , Frode Heggelund , Ronny Pedersen
CPC classification number: G06T5/002 , G06T11/40 , G06T15/503 , G06T2200/28
Abstract: When carrying out a second, higher level of anti-aliasing such as 8×MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4×MSAA, the rasterization stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.
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公开(公告)号：US09607390B2
公开(公告)日：2017-03-28
申请号：US14511540
申请日：2014-10-10
Applicant: ARM LIMITED
Inventor： Frode Heggelund , Mukesh Haresh Lahori
CPC classification number: G06T7/62 , G06T15/005
Abstract: A technique is provided for performing rasterisation of input primitives to generate graphics fragments to be processed to generate output data. The technique comprises determining a bounding box for an input primitive, and performing a multi-level patch analysis, each patch having an array of grid points defining boundaries of a set of sub-patches within that patch. The technique further comprises, when performing patch analysis of a selected patch, performing a bounding box evaluation step to determine if a condition exists where the bounding box does not cover any of the grid points, or if a special grid point coverage condition exists, and in the presence of the condition, adopting an alternative operation for that selected patch instead of a default operation. The alternative operation is configured to determine whether the primitive at least partially covers any of the sub-patches of the selected patch.
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Patent Agency Ranking
公开(公告)号：US20140168220A1
公开(公告)日：2014-06-19
申请号：US13716952
申请日：2012-12-17
Applicant: ARM Limited
Inventor： Jorn Nystad , Edvard Sorgard , Frode Heggelund
IPC: G06T15/40
Abstract: The early depth test stages 4, 13 of a graphics processing pipeline 1 are configured to broadcast information 9, 10, 11, 14 about fragments, etc., that pass those early depth tests to other stages 3, 4, 6, 12 in the pipeline. The other stages in the pipeline then use the early depth test pass information to determine if the processing of any fragments that they are currently processing can be stopped.
Abstract translation: 图形处理流水线1的早期深度测试阶段4,13被配置为将关于通过这些早期深度测试的片段等的信息9,10,11,14广播到其他阶段3,4,6,12中 管道。 管道中的其他阶段然后使用早期深度测试通过信息来确定它们当前处理的任何片段的处理是否可以被停止。
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公开(公告)号：US20130076762A1
公开(公告)日：2013-03-28
申请号：US13623751
申请日：2012-09-20
Applicant: ARM Limited
Inventor： Frode Heggelund , Aske Simon Christensen , Andreas Engh-Halstvedt
Abstract: The fragment processing pipeline 10 of a graphics processing core 2 has an associated occlusion query cache 19 that is used to maintain a set of local occlusion counters 21. The occlusion query cache 19 is maintained in a local memory 3 of the graphics processing system and can communicate via an interconnect 7 with a set of master occlusion counters 22 in a main memory 5 for the graphics processing system. When an occlusion query starts, a corresponding occlusion counter 22 is initialised in the main memory 5. A corresponding local occlusion counter 21 is also provided in the occlusion query cache 19 in the local memory 3 of the graphics processor, and is used to count the results of the occlusion query. The local occlusion counter value is written back to the occlusion counter 22 for the query in the main memory 5 at the appropriate time for further processing.
Abstract translation: 图形处理核心2的片段处理流水线10具有关联的遮挡查询高速缓存19，其用于维护一组局部遮挡计数器21.遮挡查询高速缓存19被保存在图形处理系统的本地存储器3中，并且可以 通过互连7与用于图形处理系统的主存储器5中的一组主遮挡计数器22进行通信。 当闭塞查询开始时，在主存储器5中初始化对应的遮挡计数器22.在图形处理器的本地存储器3中的遮挡查询高速缓存19中还提供相应的局部遮挡计数器21，并且用于计数 闭塞查询的结果。 局部遮挡计数器值在适当的时间被写回到主存储器5中的查询的遮挡计数器22用于进一步处理。
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公开(公告)号：US20210027533A1
公开(公告)日：2021-01-28
申请号：US16518677
申请日：2019-07-22
Applicant: Arm Limited
Inventor： Ole Magnus Ruud , Frode Heggelund
Abstract: Disclosed herein is a bounding box that can be generated for a set of one or more primitive(s) and then passed to a rasteriser circuit for use thereby when generating the graphics fragments to be processed. The bounding box generation integrates a scissor test and allows primitives for which an initial bounding box has zero intersection with a specified scissor box to be discarded, whereas for primitives whose initial bounding box does intersect the scissor box, a new bounding box can be generated for output based on the area of intersection.
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公开(公告)号：US10733782B2
公开(公告)日：2020-08-04
申请号：US16153359
申请日：2018-10-05
Applicant: Arm Limited
Inventor： Frode Heggelund , Andreas Due Engh-Halstvedt , Christian Vik Grovdal
Abstract: To perform a graphics processing operation for the entirety of an area of a render output being generated by a graphics processor, a command to draw a primitive occupying the entire area of the render output is issued to the graphics processor. The graphics processor draws the primitive by determining the vertices to use for the primitive from the area of the render output. In a tile-based graphics processor at least, the graphics processor in an embodiment also determines whether it is unnecessary to process the graphics processing command for a rendering tile and when it is determined that processing the graphics processing command for the rendering tile is unnecessary, the graphics processor omits processing the graphics processing command for the rendering tile.
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公开(公告)号：US20190108610A1
公开(公告)日：2019-04-11
申请号：US16153315
申请日：2018-10-05
Applicant: Arm Limited
Inventor： Lars Oskar Flordal , Toni Viki Brkic , Christian Vik Grovdal , Andreas Due Engh-Halstvedt , Frode Heggelund
CPC classification number: G06T1/60 , G06T1/20 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/405
Abstract: A tile-based graphics processing system comprises a graphics processing pipeline comprising a plurality of processing stages, including at least a rasteriser that rasterises input primitives to generate graphics fragments to be processed, and a renderer that processes fragments generated by the rasteriser to generate rendered fragment data, and a tile buffer configured to store data locally to the graphics processing pipeline. The graphics processing system is operable to cause data for use when performing graphics processing operations for each tile of a set of plural tiles of a plurality of tiles to be loaded into the tile buffer before causing graphics processing operations to be performed for any of the tiles of the set of plural tiles.
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