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公开(公告)号：US10748236B2
公开(公告)日：2020-08-18
申请号：US16117098
申请日：2018-08-30
Applicant: ARM Limited
Inventor： Stephane Forey , Isidoros Sideris , Reimar Gisbert Döffinger
Abstract: A warp processing unit controls, in dependence on a warp program counter shared between a plurality of threads processing respective graphics fragments, fetching of a next instruction to be executed for at least some of the plurality of threads. In response to a determination that a given subset of threads is to be discarded when at least one other subset of threads is to continue, the warp processing unit processes the given subset of threads in a discarded state. For a thread processed in the discarded state, execution of instructions continues for the discarded thread, and at least one of: generation of data access messages triggered by the discarded thread is suppressed; and at least one processing operation, which would be deferred until completion of the discarded thread had the thread not been discarded, is enabled to be commenced independently of an outcome of the discarded thread.
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公开(公告)号：US10311016B2
公开(公告)日：2019-06-04
申请号：US15607919
申请日：2017-05-30
Applicant: ARM Limited
Inventor： Frode Heggelund , Toni Viki Brkic , Reimar Gisbert Döffinger
Abstract: A graphics processing pipeline includes a rasteriser, an early culling tester, a renderer, a late culling tester, and a culling test data buffer that stores data values for use by the early and late culling testers. The testing of fragments by the early and late culling testers is controlled in accordance with a first set of state information indicative of when a culling test operation to be used to determine whether to cull the fragments is to be performed, and a second set of state information indicative of when to determine whether to update the culling test data buffer with data for the fragments based on a culling test operation, allocated to the fragments.
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3.发明授权公开(公告)号：US10832639B2
公开(公告)日：2020-11-10
申请号：US15214800
申请日：2016-07-20
Applicant: ARM LIMITED
Inventor： Toni Viki Brkic , Jakob Axel Fries , Reimar Gisbert Döffinger
Abstract: A method and an apparatus for generating a signature representative of the content of a region of an array of data in a data processing system, where the region of the array of data comprising plural data positions, and each data position having an associated data value or values. A data value or values for a data position of the region of the data array is/are generated. The data value or values for the data position of the region of the data array is/are written to storage that stores the region of the data array as it is being generated. A signature representative of the content of the region of the data array is generated in parallel with the data value or values for the data position of the region of the data array being written to the storage.
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Patent Agency Ranking
公开(公告)号：US10791332B2
公开(公告)日：2020-09-29
申请号：US14949651
申请日：2015-11-23
Applicant: ARM Limited
Inventor： Reimar Gisbert Döffinger , Thomas Nyberg
IPC: H04N19/174 , H04N19/124 , H04N19/196 , H04N19/463 , H04N19/176 , H04N19/132
Abstract: The technology described herein facilitates parallel encoding of two groups of blocks of data of a sequence of blocks of data, whilst also facilitating the use of dependent encoding across the sequence of data blocks. This is achieved by allocating pairs of first and second groups of data blocks to separate encoding units, and determining an encoding parameter value to be used for encoding the first block of each second group of data blocks. For correct reconstruction of the image, it is ensured that a block belonging to the first group of data blocks of a pair of groups of data blocks is encoded with an encoding parameter value that will cause a decoder to use the determined encoding parameter value when decoding the first block of the second group.
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5.发明授权公开(公告)号：US10789768B2
公开(公告)日：2020-09-29
申请号：US16128807
申请日：2018-09-12
Applicant: ARM Limited
Inventor： Stephane Forey , Jørn Nystad , Reimar Gisbert Döffinger , Kenneth Edvard Østby , Toni Viki Brkic
Abstract: A graphics processing apparatus comprises fragment generating circuitry to generate graphics fragments corresponding to graphics primitives, thread processing circuitry to perform threads of processing corresponding to the fragments, and forward kill circuitry to trigger a forward kill operation to prevent further processing of a target thread of processing corresponding to an earlier graphics fragment when the forward kill operation is enabled for the target thread and the earlier graphics fragment is determined to be obscured by one or more later graphics fragments. The thread processing circuitry supports enabling of the forward kill operation for a thread including at least one forward kill blocking instruction having a property indicative that the forward kill operation should be disabled for the given thread, when the thread processing circuitry has not yet reached a portion of the thread including the at least one forward kill blocking instruction.
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公开(公告)号：US20180349315A1
公开(公告)日：2018-12-06
申请号：US15607919
申请日：2017-05-30
Applicant: ARM Limited
Inventor： Frode Heggelund , Toni Viki Brkic , Reimar Gisbert Döffinger
CPC classification number: G06F15/7882 , G06T1/20 , G06T15/405
Abstract: A graphics processing pipeline includes a rasteriser, an early culling tester, a renderer, a late culling tester, and a culling test data buffer that stores data values for use by the early and late culling testers. The testing of fragments by the early and late culling testers is controlled in accordance with a first set of state information indicative of when a culling test operation to be used to determine whether to cull the fragments is to be performed, and a second set of state information indicative of when to determine whether to update the culling test data buffer with data for the fragments based on a culling test operation, allocated to the fragments.
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公开(公告)号：US20160191937A1
公开(公告)日：2016-06-30
申请号：US14949651
申请日：2015-11-23
Applicant: ARM Limited
Inventor： Reimar Gisbert Döffinger , Thomas Nyberg
IPC: H04N19/46 , H04N19/124 , H04N19/51 , H04N19/174 , H04N19/70 , H04N19/119 , H04N19/196
Abstract: The technology described herein facilitates parallel encoding of two groups of blocks of data of a sequence of blocks of data, whilst also facilitating the use of dependent encoding across the sequence of data blocks. This is achieved by allocating pairs of first and second groups of data blocks to separate encoding units, and determining an encoding parameter value to be used for encoding the first block of each second group of data blocks. For correct reconstruction of the image, it is ensured that a block belonging to the first group of data blocks of a pair of groups of data blocks is encoded with an encoding parameter value that will cause a decoder to use the determined encoding parameter value when decoding the first block of the second group.
Abstract translation: 这里描述的技术有助于数据块序列的两组数据块的并行编码，同时也有助于在数据块序列之间使用依赖编码。 这通过将第一组和第二组数据块分配给分离的编码单元并且确定要用于编码每个第二组数据块的第一块的编码参数值来实现。 为了图像的正确重建，确保属于一对数据块组的第一组数据块的块用编码参数值进行编码，该编码参数值将使解码器在解码时使用所确定的编码参数值 第二组的第一块。
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公开(公告)号：US09454844B2
公开(公告)日：2016-09-27
申请号：US14504846
申请日：2014-10-02
Applicant: ARM LIMITED
Inventor： Reimar Gisbert Döffinger
IPC: G06T15/40
CPC classification number: G06T15/405 , G06T2200/28
Abstract: An apparatus for processing graphics primitives for display includes rasterization, depth testing, and rendering circuitry. The depth testing circuitry determines if a selected graphics fragment would be obscured when displayed by comparing a depth comparison function and a depth value associated with the selected graphics fragment with a stored depth value. The depth testing circuitry suppresses rendering operations for the fragment if the selected fragment would be obscured. An update indication shows a possible change direction due to the updating for a stored depth value which depends on a received depth comparison function. The depth testing for the selected fragment is performed using the possible change direction shown by the update indication to modify the depth comparison function to allow for updating of the stored depth value by the rendering operations.
Abstract translation: 用于处理用于显示的图形基元的装置包括光栅化，深度测试和渲染电路。 深度测试电路通过将深度比较功能和与所选择的图形片段相关联的深度值与存储的深度值进行比较来确定所显示的所选择的图形片段是否会被遮蔽。 如果所选择的片段被遮蔽，则深度测试电路抑制片段的渲染操作。 更新指示示出了由于对所接收的深度比较功能而取决于所存储的深度值的更新而引起的可能的改变方向。 使用更新指示所示的可能的改变方向来执行所选片段的深度测试，以修改深度比较功能，以允许通过渲染操作来更新所存储的深度值。
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