公开(公告)号：US20200167292A1

公开(公告)日：2020-05-28

申请号：US16625102

申请日：2018-06-01

Applicant: ARM LIMITED

Inventor： Matthew James HORSNELL ,  Grigorios MAGKLIS ,  Richard Roy GRISENTHWAITE

IPC: G06F12/1027 ,  G06F9/54 ,  G06F9/46 ,  G06F12/0873

Abstract: A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.

公开(公告)号：US20170351517A1

公开(公告)日：2017-12-07

申请号：US15538365

申请日：2015-11-23

Applicant: ARM LIMITED

Inventor： Stephan DIESTELHORST ,  Michael John WILLIAMS ,  Richard Roy GRISENTHWAITE ,  Matthew James HORSNELL

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/126

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/455 ,  G06F9/46 ,  G06F9/467 ,  G06F11/362 ,  G06F11/3636 ,  G06F12/08 ,  G06F12/126

Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system.

公开(公告)号：US20170329626A1

公开(公告)日：2017-11-16

申请号：US15531836

申请日：2015-11-24

Applicant: ARM LIMITED

Inventor： Stephan DIESTELHORST ,  Matthew James HORSNELL ,  Guy LARRI

IPC: G06F9/46 ,  G06F9/52 ,  G06F9/50

Abstract: An apparatus (2) has processing circuitry (6) having access to a first processing resource (20-0) and a second processing resource (20-3). A first thread can be processed using the first processing resource. In a thread mode the second processing resource (20-3) can be used to process a second thread while in a transaction mode the second processing resource (20-3) can be used to process a transaction of the first thread comprising a number of speculatively performed operations for which results are committed at the end of the transaction. By sharing resources for supporting additional threads and supporting transactions, circuit area and power consumption can be reduced.

公开(公告)号：US20150121036A1

公开(公告)日：2015-04-30

申请号：US14585900

申请日：2014-12-30

Applicant: ARM LIMITED

Inventor： Matthew James HORSNELL ,  Richard Roy GRISENTHWAITE ,  Stuart David BILES ,  Daniel KERSHAW

IPC: G06F9/30

CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/12 ,  H04L2209/125

Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

Abstract translation: 数据处理系统2包括单指令多数据寄存器文件12和单指令多处理电路14.单指令多数据处理电路14支持执行用于执行散列算法部分的密码处理指令。 操作数存储在单指令多数据寄存器文件12中。加密支持指令不遵循正常的基于通道的处理，并且生成输出操作数，其中输出操作数的不同部分取决于输入操作数中的多个不同元素。