公开(公告)号：US20220335886A1

公开(公告)日：2022-10-20

申请号：US17723472

申请日：2022-04-19

Applicant: Au Optronics Corporation

Inventor： Ya-Jung Wang ,  Jing-Wun Jhang ,  Rong-Fu Lin ,  Nien-Chen Li ,  Hsien-Chun Wang ,  Che-Chia Chang ,  June Woo Lee ,  Hsin-Ying Lin ,  Chia-Ting Hsieh ,  Chien-Fu Huang ,  Sung-Yu Su

IPC: G09G3/32

Abstract: A pixel array is provided. The pixel array includes a plurality of pixels, wherein each of the pixels includes a light emitting diode, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to the first transistor and an anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to the second transistor. The fourth transistor is coupled to an anode of a light emitting diode of an adjacent pixel, a control terminal of the third transistor, and a cathode of the light emitting diode. The fifth transistor is coupled to the cathode of the light emitting diode, and receives a second control signal and a system low voltage.

公开(公告)号：US11355045B2

公开(公告)日：2022-06-07

申请号：US17201138

申请日：2021-03-15

Applicant: AU Optronics Corporation

Inventor： Rong-Fu Lin ,  Chi Yu ,  Chih-Fu Yang ,  Jie-Chuan Huang ,  Sung-Yu Su

IPC: G09G3/20

Abstract: A multiplexer circuit includes a first switch unit and a second switch unit. The first switch unit is electrically connected to a first data line and a first pixel circuit, and configured to turn on according to a first signal in a first time duration. The second switch unit is electrically connected to the first data line and a second pixel circuit, and configured to turn on according to a second signal in a second time duration. The first time duration and the second time duration substantially start or end at a same time, so that the first time duration and the second time duration have overlap.

公开(公告)号：US11264413B2

公开(公告)日：2022-03-01

申请号：US16535067

申请日：2019-08-08

Applicant: Au Optronics Corporation

Inventor： Yu-Min Chi ,  Sung-Yu Su ,  Pin-Miao Liu

IPC: H01L27/12 ,  G02F1/1335 ,  G02F1/1362 ,  G02F1/1368

Abstract: A display device includes a substrate, a first data line, a scan line, a first sub-pixel, a passivation layer, and a common electrode. The first sub-pixel includes a first main-driving element, a first sub-driving element, a first capacitor electrode, and a first pixel electrode. The first main-driving element includes a first main-gate, a first main-channel layer, a first main-source, and a first main-drain. The first sub-driving element includes a first sub-gate, a first sub-channel layer, a first sub-source, and a first sub-drain. The first capacitor electrode is electrically connected with the first main-drain and the first sub-source. The first pixel electrode is electrically connected with the first sub-drain. The common electrode and the first capacitor electrode have a first main capacitor therebetween. The common electrode and the first pixel electrode have a first sub capacitor therebetween.

公开(公告)号：US11011105B2

公开(公告)日：2021-05-18

申请号：US16828928

申请日：2020-03-24

Applicant: Au Optronics Corporation

Inventor： Hsien-Chun Wang ,  Ya-Jung Wang ,  Jing-Wun Jhang ,  Chen-Feng Fan ,  Wan-Heng Chang ,  Sung-Yu Su

IPC: G09G3/32

Abstract: A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.

公开(公告)号：US20210104192A1

公开(公告)日：2021-04-08

申请号：US16871066

申请日：2020-05-11

Applicant: Au Optronics Corporation

Inventor： Shu-Hao Huang ,  Sung-Yu Su

IPC: G09G3/20

Abstract: A pixel array substrate including a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixels, a first multiplexer, a second multiplexer, a first connecting line and a second connecting line is provided. The substrate has a display area. The first signal lines are arranged on the substrate and define a first row region and a second row region of the display area. The pixels are arranged into a first pixel row and a second pixel row which are respectively disposed in the first row region and the second row region. The first multiplexer is disposed in the first row region and electrically connected to a part of the second signal lines. The second multiplexer is disposed in the second row region and electrically connected to another part of the second signal lines. The first connecting line is electrically connected to the first multiplexer. The second connecting line is electrically connected to the second multiplexer. The electrical resistivity of the first connecting line and the second connecting line is greater than the electrically resistivity of the first signal lines and the second signal lines.

公开(公告)号：US10971093B2

公开(公告)日：2021-04-06

申请号：US16239686

申请日：2019-01-04

Applicant: AU OPTRONICS CORPORATION

Inventor： Peng-Bo Xi ,  Sung-Yu Su ,  Chen-Feng Fan ,  Wan-Heng Chang

IPC: G09G3/36

Abstract: A pixel circuit includes a storage capacitor, a first switch, and a second switch. The first switch is electrically connected to a first end of the storage capacitor, and configured to provide a data voltage to the first end of the storage capacitor according to a gate signal. The second switch is electrically connected between the first end of the storage capacitor and a second end of the storage capacitor, and configured to receive a first operating voltage from the second end of the storage capacitor and provide the first operating voltage to the first end of the storage capacitor.

公开(公告)号：US10916181B2

公开(公告)日：2021-02-09

申请号：US16700855

申请日：2019-12-02

Applicant: AU Optronics Corporation

Inventor： Rong-Fu Lin ,  Kai-Wei Hong ,  Jie-Chuan Huang ,  Peng-Bo Xi ,  Sung-Yu Su

IPC: G06F3/038 ,  G09G5/00 ,  G09G3/20 ,  G06F3/041

Abstract: A display device comprising an active area and a surrounding area is provided. The active area includes a common electrode for receiving a common voltage. The surrounding area is located at a side of the active area, and the surrounding area includes a shielding metal layer and a surrounding circuit. The shielding metal layer is electrically isolated from the common electrode and receives a shielding voltage. The surrounding circuit and a first shielding metal are overlapped in a vertical projection direction, and the common voltage is power-isolated from the shielding voltage.

公开(公告)号：US20200185432A1

公开(公告)日：2020-06-11

申请号：US16792291

申请日：2020-02-16

Applicant: Au Optronics Corporation

Inventor： Shu-Hao Huang ,  Chin-Chuan Liu ,  Sung-Yu Su

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1333

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed. Another photolithography and etching process is performed by using said photo mask to form first to third openings and a via hole in the second interlayered insulation layer, wherein along a normal direction, the third opening and the first contact hole are overlapped, the via hole and the second contact hole are overlapped, the first opening and the third contact hole are overlapped, and the second opening and the fourth contact hole are overlapped.

公开(公告)号：US10559274B2

公开(公告)日：2020-02-11

申请号：US15437589

申请日：2017-02-21

Applicant: AU Optronics Corporation

Inventor： Peng-Bo Xi ,  Sung-Yu Su

IPC: G09G3/00 ,  G09G5/00 ,  G09G3/20 ,  G09G3/36 ,  H03K17/693 ,  H03K17/00

Abstract: A multiplexer is provided herein. The multiplexer has a plurality of first driving units and a plurality of second driving units. Each of the first driving units has a first data voltage input terminal, and each of the second driving units has a second data voltage input terminal. The first data voltage input terminal and the second data voltage input terminal are configured to receive pixel voltage signals with different polarities. In the first driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a first reset signal, wherein the transistor of the first driving unit is coupled to the first data voltage input terminal and a first data line. In the second driving unit, a voltage difference between a gate and a drain of a transistor is controlled by a second reset signal, wherein the transistor of the second driving unit is coupled to the second data voltage input terminal and a second data line.

公开(公告)号：US10296120B2

公开(公告)日：2019-05-21

申请号：US15678623

申请日：2017-08-16

Applicant: AU Optronics Corporation

Inventor： Peng-Bo Xi ,  Sung-Yu Su

IPC: G06F3/041 ,  G06F3/044 ,  G02F1/13 ,  G09G3/36 ,  G02F1/1343

Abstract: A touch display panel and a driving method thereof are disclosed. The touch display panel includes a plurality of pixels, a plurality of viewing angle control (VAC) electrode units, and a plurality of touch receiving electrode units. Each pixel includes a pixel electrode and a common electrode. At least one of the pixel electrode and the common electrode has a plurality of slits. The VAC electrode units are arranged along a first direction. Each VAC electrode unit includes a plurality of first VAC electrode series and a plurality of second VAC electrode series, and each first VAC electrode series and each second VAC electrode series are alternately arranged along the first direction. The touch receiving electrode units are arranged along the second direction, and the VAC electrode units and the touch receiving electrode unit form a touch unit.