公开(公告)号：US06860711B2

公开(公告)日：2005-03-01

申请号：US10187670

申请日：2002-07-01

申请人： Takayuki Yamagishi

发明人： Takayuki Yamagishi

IPC分类号： H01L21/677 ,  H01L21/205 ,  H01L21/68 ,  H01L21/687 ,  B65G49/07

CPC分类号： H01L21/67745 ,  H01L21/68742 ,  Y10S414/141

摘要： A semiconductor-manufacturing device is equipped with a load-lock chamber and a reactor, which are directly connected, wherein a semiconductor wafer is transferred by a transferring arm provided inside the load-lock chamber from the load-lock chamber onto a susceptor provided inside the reactor. The device includes a buffer mechanism for keeping a semiconductor wafer standing by inside the reactor. The buffer mechanism includes at least two supporting means, which are provided around the susceptor to support the semiconductor wafer and which rotate in a horizontal direction, a shaft means for supporting the supporting means in a vertical direction, a rotating mechanism for rotating the supporting means coupled to the shaft means, and an elevating means for moving the shaft means up and down.

摘要翻译： 半导体制造装置配备有直接连接的负载锁定室和电抗器，其中半导体晶片由设置在负载锁定室内的传送臂从负载锁定室传送到设置在内部的基座上 反应堆。 该装置包括用于将半导体晶片保持在反应器内部的缓冲机构。 缓冲机构包括至少两个支撑装置，其设置在基座周围以支撑半导体晶片并且在水平方向上旋转，用于在垂直方向上支撑支撑装置的轴装置，用于使支撑装置旋转的旋转机构 联接到轴装置，以及用于上下移动轴装置的升降装置。

公开(公告)号：US09793148B2

公开(公告)日：2017-10-17

申请号：US13166367

申请日：2011-06-22

申请人： Takayuki Yamagishi ,  Masaei Suwada ,  Hiroyuki Tanaka

发明人： Takayuki Yamagishi ,  Masaei Suwada ,  Hiroyuki Tanaka

IPC分类号： H01L21/68 ,  H01L21/687

CPC分类号： H01L21/681 ,  H01L21/68742

摘要： A method for positioning wafers in dual wafer transport, includes: simultaneously moving first and second wafers placed on first and second end-effectors to positions over lift pins protruding from first and second susceptors, respectively; and correcting the positions of the first and second wafers without moving any of the lift pins relative to the respective susceptors or without moving the lift pins relative to each other, wherein when the first and second wafers are moved to the respective positions, the distance between the first wafer and tips of the lift pins of the first susceptor is substantially smaller than the distance between the second wafer and tips of the lift pins of the second susceptor.

公开(公告)号：US07638003B2

公开(公告)日：2009-12-29

申请号：US11330662

申请日：2006-01-12

申请人： Kiyoshi Satoh ,  Takayuki Yamagishi

发明人： Kiyoshi Satoh ,  Takayuki Yamagishi

IPC分类号： C23C16/00 ,  C23F1/00 ,  H01L21/306

CPC分类号： C23C16/4586

摘要： A semiconductor processing apparatus includes: a reaction chamber; a susceptor disposed in the reaction chamber for placing a substrate thereon and having through-holes in an axial direction of the susceptor; lift pins slidably disposed in the respective through-holes for lifting the substrate over the susceptor; and a means for reducing contact resistance between the lift pins and the respective through-holes.

摘要翻译： 半导体处理装置包括：反应室; 设置在所述反应室中的基座，用于在其上放置基板并在所述基座的轴向方向上具有通孔; 可滑动地设置在各个通孔中的提升销，用于将基板提升到基座上; 以及用于降低提升销和各个通孔之间的接触电阻的装置。

公开(公告)号：US07021881B2

公开(公告)日：2006-04-04

申请号：US11021311

申请日：2004-12-23

申请人： Takayuki Yamagishi ,  Masaei Suwada ,  Takeshi Watanabe

发明人： Takayuki Yamagishi ,  Masaei Suwada ,  Takeshi Watanabe

IPC分类号： B65G49/07

CPC分类号： H01L21/67742 ,  H01L21/67748 ,  Y10S414/139

摘要： Semiconductor processing equipment that has increased efficiency, throughput, and stability, as well as reduced operating cost, footprint, and faceprint is provided. Other than during deposition, the atmosphere of both the reaction chamber and the transfer chamber are evacuated using the transfer chamber exhaust port, which is located below the surface of the semiconductor wafer. This configuration prevents particles generated during wafer transfer or during deposition from adhering to the surface of the semiconductor wafer. Additionally, by introducing a purge gas into the transfer chamber during deposition, and by using an insulation separating plate 34, the atmospheres of the transfer and reaction chambers can be effectively isolated from each other, thereby preventing deposition on the walls and components of the transfer chamber. Finally, the configuration described herein permits a wafer buffer mechanism to be used with the semiconductor processing equipment, thereby further increasing throughput and efficiency.

摘要翻译： 提供了提高效率，吞吐量和稳定性以及降低运营成本，占地面积和面部印刷的半导体处理设备。 除了沉积之外，使用位于半导体晶片表面下方的转移室排气口将反应室和转移室的气氛抽真空。 这种构造防止在晶片转移期间或在沉积期间产生的颗粒粘附到半导体晶片的表面。 此外，通过在沉积期间将吹扫气体引入转移室，并且通过使用绝缘分隔板34，可以有效地将转移室和反应室的气氛彼此隔离，从而防止沉积在转移的壁和组分上 房间。 最后，本文描述的配置允许晶片缓冲机构与半导体处理设备一起使用，从而进一步提高吞吐量和效率。

公开(公告)号：US06955741B2

公开(公告)日：2005-10-18

申请号：US10214890

申请日：2002-08-07

申请人： Takayuki Yamagishi

发明人： Takayuki Yamagishi

IPC分类号： H01L21/683 ,  C23C16/458 ,  H01L21/687 ,  H01L21/00 ,  C23C16/00

CPC分类号： H01L21/68742 ,  C23C16/4583

摘要： The present application provides a PECVD reaction chamber for processing semiconductor wafers comprising a susceptor for supporting a semiconductor wafer inside the reaction chamber wherein the susceptor comprises a plurality vertical through-bores, a moving means for moving the susceptor vertically between at least a first position and a second position, wafer-lift pins passing through the through-bores wherein the lower end of each wafer pin is attached to a lift member, and a lift member linked with an elevating mechanism for moving the wafer-lift pins vertically. The disclosed apparatus reduces contamination on the underside of the semiconductor wafer.

摘要翻译： 本申请提供了一种用于处理半导体晶片的PECVD反应室，其包括用于在反应室内支撑半导体晶片的基座，其中基座包括多个垂直通孔;移动装置，用于在至少第一位置和 第二位置，通过通孔的晶片升降销，其中每个晶片销的下端附接到提升构件，以及与用于垂直移动晶片升降销的升降机构连接的提升构件。 所公开的装置减少了半导体晶片的下侧的污染。

公开(公告)号：US06945746B2

公开(公告)日：2005-09-20

申请号：US10371050

申请日：2003-02-20

申请人： Takayuki Yamagishi ,  Takeshi Watanabe ,  Masaei Suwada

发明人： Takayuki Yamagishi ,  Takeshi Watanabe ,  Masaei Suwada

IPC分类号： H01L21/677 ,  H01L21/00 ,  H01L21/02 ,  B65G49/07

CPC分类号： H01L21/67196 ,  Y10S414/135

摘要： The equipment comprises a semiconductor-processing device in which a load-lock chamber, a transfer chamber and a reaction chamber are modularized into, a main frame, a stand-alone chamber frame on which the semiconductor-processing device is placed, a sliding mechanism for enabling attaching/removing of the chamber frame to/from the main frame smoothly, and a positioning mechanism for fixing a position of the chamber frame. This enables the processing device to be attached and removed at will. The method comprises pulling out from the main frame the chamber frame, on which the modularized semiconductor-processing device is placed; forming a maintenance space inside the main frame; maintaining the semiconductor-processing device and peripherals attached in the vicinity of the main frame, and putting the chamber frame with the processing device back into the main frame.

摘要翻译： 该设备包括半导体处理装置，其中负载锁定室，传送室和反应室被模块化成主框架，其上放置半导体处理装置的独立室框架，滑动机构 用于能够平稳地将主框架安装/拆卸到主框架上;以及定位机构，用于固定室框架的位置。 这使得可以随意地附接和移除处理装置。 该方法包括从主框架拉出放置有模块化半导体处理装置的腔室框架; 在主框架内形成维护空间; 保持附着在主框架附近的半导体处理装置和外围设备，以及将处理装置的室框架放回到主框架中。

公开(公告)号：US20050118001A1

公开(公告)日：2005-06-02

申请号：US11021311

申请日：2004-12-23

申请人： Takayuki Yamagishi ,  Masaei Suwada ,  Takeshi Watanabe

发明人： Takayuki Yamagishi ,  Masaei Suwada ,  Takeshi Watanabe

IPC分类号： C23C16/44 ,  B65G49/07 ,  H01L21/677 ,  B65G1/00

CPC分类号： H01L21/67742 ,  H01L21/67748 ,  Y10S414/139

摘要： Semiconductor processing equipment that has increased efficiency, throughput, and stability, as well as reduced operating cost, footprint, and faceprint is provided. Other than during deposition, the atmosphere of both the reaction chamber and the transfer chamber are evacuated using the transfer chamber exhaust port, which is located below the surface of the semiconductor wafer. This configuration prevents particles generated during wafer transfer or during deposition from adhering to the surface of the semiconductor wafer. Additionally, by introducing a purge gas into the transfer chamber during deposition, and by using an insulation separating plate 34, the atmospheres of the transfer and reaction chambers can be effectively isolated from each other, thereby preventing deposition on the walls and components of the transfer chamber. Finally, the configuration described herein permits a wafer buffer mechanism to be used with the semiconductor processing equipment, thereby further increasing throughput and efficiency.

摘要翻译： 提供了提高效率，吞吐量和稳定性以及降低运营成本，占地面积和面部印刷的半导体处理设备。 除了沉积之外，使用位于半导体晶片表面下方的转移室排气口将反应室和转移室的气氛抽真空。 这种构造防止在晶片转移期间或在沉积期间产生的颗粒粘附到半导体晶片的表面。 此外，通过在沉积期间将吹扫气体引入转移室，并且通过使用绝缘分隔板34，可以有效地将转移室和反应室的气氛彼此隔离，从而防止沉积在转移的壁和组分上 房间。 最后，本文描述的配置允许晶片缓冲机构与半导体处理设备一起使用，从而进一步提高吞吐量和效率。

公开(公告)号：US06454516B1

公开(公告)日：2002-09-24

申请号：US09612739

申请日：2000-07-10

申请人： Takayuki Yamagishi

发明人： Takayuki Yamagishi

IPC分类号： B65G4907

CPC分类号： H01L21/67265 ,  H01L21/687 ,  Y10S414/136

摘要： There is provided an aligner apparatus and method which can align a semiconductor substrate without contaminating a rear surface. The aligner apparatus for arbitrarily aligning the circular semiconductor substrate having a notch or “orifla” at an edge portion includes at least three spindle units rotatably axially supported by a plate, holding units for holding the semiconductor substrate, attached to respective tip ends of the spindle units, a rotation mechanism for rotating the spindle units, and a sensor for detecting the notch or “orifla”. An edge portion of the semiconductor substrate is brought into contact with the respective holding units, so that the semiconductor substrate is held. When the spindle units rotate, the semiconductor substrate held by the holding units rotates around its axial line.

摘要翻译： 提供了一种可以对准半导体衬底而不污染后表面的对准器装置和方法。 用于任意对齐在边缘部分具有凹口或“凸缘”的圆形半导体衬底的对准器装置包括至少三个主轴单元，其被可旋转地轴向支撑在板上，用于保持半导体衬底的保持单元，附接到主轴的相应末端 单元，用于旋转主轴单元的旋转机构，以及用于检测凹口或“口”的传感器。 半导体衬底的边缘部分与各个保持单元接触，从而保持半导体衬底。 当主轴单元旋转时，由保持单元保持的半导体基板围绕其轴线旋转。