公开(公告)号：US11729300B2

公开(公告)日：2023-08-15

申请号：US17163211

申请日：2021-01-29

Applicant: Amazon Technologies, Inc.

Inventor： Thomas A. Volpe ,  Timothy David Gasser ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Vithal Dattatraya Shirodkar

IPC: H04L69/22 ,  H04L45/7453

CPC classification number: H04L69/22 ,  H04L45/7453

Abstract: Programmatically defined fields of metadata for a network packet may be generated. Instructions indicating different portions of data from different headers of a network packet may be stored at a packet processor. When a network packet is received, the different portions of the data may be extracted from the different headers of the packet according to the instructions and provided to other stages of the packet processor for processing. Different portions of the same programmatically defined field may be utilized at different stages in the packet processor. The programmatically defined field may be used to generate a hash value that selects an entry in a lookup table describing a forwarding decision for a network packet.

公开(公告)号：US20230018032A1

公开(公告)日：2023-01-19

申请号：US17952144

申请日：2022-09-23

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US10963001B1

公开(公告)日：2021-03-30

申请号：US15669810

申请日：2017-08-04

Applicant: Amazon Technologies, Inc.

Inventor： Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Nafea Bshara ,  Asif Khan

IPC: G06F1/08 ,  G06F1/12 ,  H04L29/08 ,  G06F9/455

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating clock information with the client configurable logic for various purposes.

公开(公告)号：US10911292B1

公开(公告)日：2021-02-02

申请号：US15637568

申请日：2017-06-29

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Robert Michael Johnson ,  Asif Khan ,  Stanislav Spassov ,  Christopher Joseph Pettey

IPC: H04L29/08 ,  H04L29/00 ,  H04L12/26 ,  H04M11/08 ,  G06F9/00 ,  H04M11/06

Abstract: Access control is provided for peer-to-peer communication between a source peripheral device and a destination peripheral device without going through a host device. The access control mechanism can allow or block a request for a transaction to go out via a port of the source peripheral device to the destination peripheral device by comparing an attribute associated with the transaction with a filter attribute stored in memory. Embodiments of the disclosed technologies can allow programming of different filter attributes for different tenants in a multi-tenant environment.

公开(公告)号：US20200257454A1

公开(公告)日：2020-08-13

申请号：US16863700

申请日：2020-04-30

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Erez Izenberg ,  Robert Michael Johnson ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Nafea Bshara ,  Christopher Joseph Pettey

IPC: G06F3/06 ,  G06F15/78 ,  G06F21/51 ,  G06F13/28 ,  G11C7/10

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

公开(公告)号：US10705995B2

公开(公告)日：2020-07-07

申请号：US16361007

申请日：2019-03-21

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US10346337B1

公开(公告)日：2019-07-09

申请号：US14673466

申请日：2015-03-30

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

Abstract: An Input/Output (I/O) adapter device coupled to a host device can perform data mirroring or data striping of payload data for transmitting to multiple network destinations. In some embodiments, a virtual machine running on the host device or on the I/O adapter device may be aware of the capabilities of the I/O adapter device to perform data mirroring or data striping and configure the I/O adapter device for performing data mirroring or data striping operations. In some embodiments, a virtual machine may be agnostic to the capabilities of the I/O adapter device to perform data mirroring or data striping and the I/O adapter device may perform data mirroring or data striping “under the hood” or without being configured by the virtual machine.

公开(公告)号：US10203967B1

公开(公告)日：2019-02-12

申请号：US15669806

申请日：2017-08-04

Applicant: Amazon Technologies, Inc.

Inventor： Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Asif Khan ,  Robert Michael Johnson

IPC: G06F13/10 ,  G06F9/445 ,  G06F9/455

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include associating manifests with the client configurable logic for various purposes.

公开(公告)号：US10185671B1

公开(公告)日：2019-01-22

申请号：US14983145

申请日：2015-12-29

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Robert Michael Johnson

IPC: G06F13/16 ,  G06F13/40

Abstract: A controller is configured to transmit a broadcast write request on at least one bus. The broadcast write request includes an address and a value. A first logic module determines that the broadcast write request is targeting the first logic module. The first logic module stores the value at a first addressed register specified by the register address. The second logic module determines that the broadcast write request is targeting the second logic module. The second logic module stores the value at a second addressed register specified by the register address. The first and second logic modules are connected to the at least one bus.

公开(公告)号：US10049001B1

公开(公告)日：2018-08-14

申请号：US14671800

申请日：2015-03-27

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Thomas A. Volpe

IPC: G06F11/10 ,  G06F9/455 ,  G06F11/08 ,  H03M13/03 ,  G06F9/46 ,  H03M13/05

Abstract: Server computers often include one or more input/output (I/O) devices for communicating with a network or direct attached storage device. Data written to or read from storage devices may acquire errors in transit. The I/O adapter device may implement processes to generate or check error correction values, where the error correction values are provided to verify the correctness of the written or read value. The I/O adapter device may determine the portion of the data to be used in calculating the error correction value in a flexible and configurable manner.