公开(公告)号：US08397199B2

公开(公告)日：2013-03-12

申请号：US12762861

申请日：2010-04-19

申请人： Apurva H. Soni ,  Antonietta Oliva ,  Edgardo F. Klass ,  Matthew J. T. Page ,  James E. Burnette, II

发明人： Apurva H. Soni ,  Antonietta Oliva ,  Edgardo F. Klass ,  Matthew J. T. Page ,  James E. Burnette, II

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).

摘要翻译： 在一个实施例中，老化分析工具可以被配置为识别根据最坏情况的应力向量和/或设计者识别的最坏情况条件预期会经历老化效应的晶体管。 老化分析工具可以修改电路的表示（例如网表），用老化的晶体管代替所识别的晶体管（例如通过修改网表中的晶体管的参数）。 老化分析工具可以在电路预期运行的一系列条件下处理修改的网表，以确保设计在老化后符合规格。 该过程可以重复，直到老化设计符合规格（由设计者进行的电路改进以改进设计）。

公开(公告)号：US08327310B1

公开(公告)日：2012-12-04

申请号：US13177916

申请日：2011-07-07

申请人： Antonietta Oliva ,  Gregory S. Scott ,  Edgardo F. Klass ,  Vincent R. von Kaenel

发明人： Antonietta Oliva ,  Gregory S. Scott ,  Edgardo F. Klass ,  Vincent R. von Kaenel

IPC分类号： G06F11/22 ,  G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5036

摘要： A software tool and method for analyzing the reliability or failure rate of an integrated circuit (IC) are disclosed. The IC may include a plurality of circuit designs, and the software tool and method may aid a designer of the IC in determining a reliability rating of the IC based on reliability ratings of transistors or other circuit devices used in the circuit designs. In particular, the IC may include one or more circuit designs that have multiple instances within the IC (i.e., the same circuit design is instantiated multiple times), and the software tool and method may take into account the multiple instances when determining the reliability rating of the IC.

摘要翻译： 公开了一种用于分析集成电路（IC）的可靠性或故障率的软件工具和方法。 IC可以包括多个电路设计，并且该软件工具和方法可以帮助IC的设计者基于在电路设计中使用的晶体管或其它电路器件的可靠性等级来确定IC的可靠性等级。 特别地，IC可以包括在IC内具有多个实例的一个或多个电路设计（即，相同的电路设计被实例化多次），并且当确定可靠性等级时，软件工具和方法可以考虑多个实例 的IC。

公开(公告)号：US06617231B1

公开(公告)日：2003-09-09

申请号：US10091789

申请日：2002-03-06

申请人： Alfred J. Griffin, Jr. ,  Antonietta Oliva ,  Adel El Sayed

发明人： Alfred J. Griffin, Jr. ,  Antonietta Oliva ,  Adel El Sayed

IPC分类号： H01L2144

CPC分类号： H01L21/28556 ,  H01L21/76843 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process whereby elimination of metal extrusion through the via-barrier layer into the base of etched via holes is accomplished by controlling the process temperature of the via-barrier deposition to less than 400° C., and preferably to about 380° C. By eliminating the cause of metal extrusions, i.e., excessive thermally induced stresses on the metal confined biaxially by the dielectric via walls, the resulting defect-free vias are independent of the barrier thickness. The method is applicable to different metal stacks, and in turn, yield and reliability of the device is significantly enhanced.