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公开(公告)号：US08410814B2
公开(公告)日：2013-04-02
申请号：US13162360
申请日：2011-06-16
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C7/067 , G11C7/1084
摘要： Receiver circuits for differential and single-ended signals are disclosed. In some embodiments, a receiver may include a first amplifier configured to receive a first signal of a differential pair of signals at a first input and a second signal of the differential pair of signals at a second input when operating in differential mode. The receiver may also include a second amplifier coupled to the first amplifier, where the second amplifier is configured to receive a reference signal at a third input and a single-ended signal at the first input when operating in single-ended mode. In some embodiments, several receivers may be used, for example, to process a differential clock signal and one or more single-ended data signals referenced to the clock signal and/or differential data signals referenced to a single-ended clock signal. In some embodiments, the delays of each signal propagating through each respective receiver may be independently adjusted.
摘要翻译： 公开了用于差分和单端信号的接收器电路。 在一些实施例中，接收机可以包括第一放大器，其被配置为当在差分模式下操作时在第一输入处接收差分信号对的第一信号和在第二输入处的差分信号对的第二信号。 接收机还可以包括耦合到第一放大器的第二放大器，其中第二放大器被配置为在单端模式下操作时在第三输入处接收参考信号和第一输入端的单端信号。 在一些实施例中，可以使用几个接收器来处理差分时钟信号和以参考单端时钟信号的时钟信号和/或差分数据信号参考的一个或多个单端数据信号。 在一些实施例中，可以独立地调整通过每个相应接收机传播的每个信号的延迟。
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公开(公告)号：US20120299653A1
公开(公告)日：2012-11-29
申请号：US13115824
申请日：2011-05-25
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/72 , H03F2203/7236 , H04L25/0272 , H04L25/0292
摘要： Receiver circuits for differential and single-ended signals are disclosed. A receiver may include a differential amplifier configured to receive a first signal of a differential pair at a first input and a second signal of the differential pair at a second input when operating in differential mode, and a single-ended signal at the first input and a reference signal at a third input when operating in single-ended mode. The receiver may also include an inverter coupled to the differential amplifier. The inverter may be configured to provide a first beta ratio in differential mode and a second beta ratio in single-ended mode. Several receivers may be used, for example, to process a differential clock signal and one or more single-ended data signals referenced to the clock signal and/or differential data signals referenced to a single-ended clock signal. The rise/fall delays of each signal through each respective receiver may be independently adjusted.
摘要翻译： 公开了用于差分和单端信号的接收器电路。 接收机可以包括差分放大器，其被配置为当在差分模式下操作时在第一输入处接收差分对的第一信号和在第二输入处的差分对的第二信号，以及在第一输入处接收单端信号， 在单端模式下工作在第三输入时的参考信号。 接收器还可以包括耦合到差分放大器的反相器。 逆变器可以被配置为在单端模式中提供差分模式下的第一β比和第二β比。 可以使用几个接收器来处理差分时钟信号以及以参考单端时钟信号的时钟信号和/或差分数据信号为参考的一个或多个单端数据信号。 每个信号通过每个相应接收机的上升/下降延迟可以被独立地调整。
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公开(公告)号：US20120250427A1
公开(公告)日：2012-10-04
申请号：US13182952
申请日：2011-07-14
CPC分类号： G06F13/4072
摘要： An interface circuit having a first signal path and a second signal path is disclosed. The first and second signal paths are coupled between a first and second nodes, wherein the first node is coupled to receive signals from a source external to an integrated circuit upon which the interface circuit is implemented. Each of the first and second signal paths include circuitry implemented with transistors rated at higher voltages than internal circuitry coupled to receive signals therefrom. The first and second signal paths may utilize different circuit topologies. The interface may thus be used in environments where external circuitry coupled to the external input node conforms to one of a number of different standards (e.g., LPDDR1 and LPDDR2).
摘要翻译： 公开了一种具有第一信号路径和第二信号路径的接口电路。 第一和第二信号路径耦合在第一和第二节点之间，其中第一节点被耦合以从实现接口电路的集成电路的外部的源接收信号。 第一信号路径和第二信号路径中的每一个包括以与内部电路相比额定高于内部电路的晶体管实现的电路，耦合到从其接收信号。 第一和第二信号路径可以利用不同的电路拓扑。 因此，接口可以用于耦合到外部输入节点的外部电路符合多个不同标准（例如，LPDDR1和LPDDR2）之一的环境中。
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公开(公告)号：US20120086484A1
公开(公告)日：2012-04-12
申请号：US12901745
申请日：2010-10-11
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L7/0818 , H03L7/089 , H03L7/10
摘要： A delay locked loop (DLL) includes a delay line configured to provide a delayed version of a reference clock as a feedback clock. The DLL also includes a phase detector that may provide an output signal that is indicative of a change in a delay associated with the delay line. The DLL may also include a step size controller that may provide a step size indication corresponding to a first step size in response to detecting the output signal indicating a first change in delay, and to provide a step size indications corresponding to a second step size that is smaller than the first step size in response to detecting the output signal indicating a second change in delay.
摘要翻译： 延迟锁定环（DLL）包括延迟线，其被配置为将参考时钟的延迟版本提供为反馈时钟。 该DLL还包括相位检测器，其可以提供指示与延迟线相关联的延迟的变化的输出信号。 DLL还可以包括步长控制器，其可以响应于检测到指示延迟的第一改变的输出信号而提供对应于第一步长的步长指示，并且提供对应于第二步长的步长大小指示 响应于检测到指示延迟的第二改变的输出信号，小于第一步长。
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公开(公告)号：US20120083052A1
公开(公告)日：2012-04-05
申请号：US13323168
申请日：2011-12-12
IPC分类号： H01L21/66
CPC分类号： H01L25/105 , H01L22/32 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L24/05 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/82 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/13144 , H01L2224/1319 , H01L2224/16225 , H01L2224/24225 , H01L2224/32145 , H01L2224/48227 , H01L2224/82101 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06596 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/0102 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ICs (in non-flip chip orientation), and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other ICs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. A second set of pads may be connected to package pins for package-on-package solutions. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size.
摘要翻译： 在一个实施例中，提供了一种用于应用集成电路（IC）和一个或多个其它IC的封装解决方案。 封装解决方案可以支持应用IC的片上芯片封装（与封装基板的倒装芯片连接）和其他IC（非倒装芯片方向）以及应用IC封装封装封装 和其他IC。 封装衬底可以包括靠近应用IC的第一组焊盘，以支持与其它IC的片上芯片连接。 焊盘可以连接到延伸在应用IC下面的导体，以连接到应用IC。 第二组焊盘可以连接到封装封装解决方案的封装引脚。 如果片上芯片解决方案证明是可靠的，则可以消除对封装封装解决方案的支持，并且可以减小封装衬底的尺寸。
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公开(公告)号：US08134874B2
公开(公告)日：2012-03-13
申请号：US12355389
申请日：2009-01-16
申请人： Shinye Shiu , Vincent R. von Kaenel
发明人： Shinye Shiu , Vincent R. von Kaenel
IPC分类号： G11C7/10
CPC分类号： G11C11/413
摘要： A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a voltage supply node, and a comparator may be coupled to compare a voltage level present on the virtual voltage rail to a reference voltage to thereby provide an output signal based on the comparison. The switching circuit may be configured to electrically couple the virtual voltage rail to the voltage supply node depending upon the output signal. In some embodiments, the switching circuit may be implemented using either a PMOS transistor or an NMOS transistor, although other embodiments may employ other switching circuits.
摘要翻译： 公开了包括耦合到虚拟电压轨的多个存储单元的存储器电路。 多个存储单元可以形成例如SRAM阵列的子阵列。 开关电路可以耦合在虚拟电压轨和电压供应节点之间，并且比较器可以被耦合以将存在于虚拟电压轨上的电压电平与参考电压进行比较，从而基于该比较来提供输出信号。 开关电路可以被配置为根据输出信号将虚拟电压轨电耦合到电压供应节点。 在一些实施例中，可以使用PMOS晶体管或NMOS晶体管来实现开关电路，尽管其他实施例可以采用其他开关电路。
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公开(公告)号：US20110255351A1
公开(公告)日：2011-10-20
申请号：US13171781
申请日：2011-06-29
CPC分类号： H03K3/012 , H03K3/35613
摘要： In one embodiment, a level shifter circuit may include a shift stage that also embeds transistors that implement a logic operation on two or more inputs to the level shifter. At least one of the inputs may be sourced from circuitry that is powered by a different power supply than the level shifter and circuitry that receives the level shifter output. Additionally, the level shifter includes one or more dummy transistors that match transistors the perform the logic operation, to improve symmetry of the level shifter circuit. In some embodiments, certain design and layout rules may be applied to the level shifter circuit to limit variation in the symmetry over various manufacturing variations.
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公开(公告)号：US20110156693A1
公开(公告)日：2011-06-30
申请号：US13046103
申请日：2011-03-11
IPC分类号： G01R23/02
CPC分类号： G06F1/3203 , G01R31/2879 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.
摘要翻译： 在一个实施例中，集成电路包括至少一个测量单元，其被配置为产生指示集成电路可用于给定工作频率的电源电压的输出，以及耦合以接收输出的控制单元。 控制单元被配置为响应于输出而产生指示集成电路的所请求的电源电压的电压控制输出。 电压控制输出可以从集成电路输出供集成电路外部的电路使用，以便为集成电路产生电源电压。
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公开(公告)号：US07961007B2
公开(公告)日：2011-06-14
申请号：US12433823
申请日：2009-04-30
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/018514
摘要： In one embodiment, a receiver circuit is provide that may receive either a differential input or a single-ended input corresponding to an interface. The receiver circuit may include at least two current sources to control a gain of an amplification stage in the receiver. If the receiver circuit is receiving a differential input, one of the current sources may be used. If the receiver circuit is receiving a single-ended input, both of the current sources may be used. A larger gain may thus be provided for the single-ended input as compared to the differential input.
摘要翻译： 在一个实施例中，提供可以接收对应于接口的差分输入或单端输入的接收机电路。 接收器电路可以包括至少两个电流源以控制接收器中的放大级的增益。 如果接收器电路正在接收差分输入，则可以使用其中一个电流源。 如果接收器电路正在接收单端输入，则可以使用两个电流源。 因此与差分输入相比，可以为单端输入提供更大的增益。
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公开(公告)号：US07834599B2
公开(公告)日：2010-11-16
申请号：US12486891
申请日：2009-06-18
CPC分类号： G06F1/26 , H02J7/345 , Y10S323/901
摘要： In one embodiment, an apparatus is provided for a system including an integrated circuit coupled to a node to receive a supply voltage and having bypass capacitors coupled in parallel with the integrated circuit to the node. The apparatus comprises a first capacitor, a switch coupled to the first capacitor, and a voltage source configured to charge the first capacitor. The switch is coupled to receive a control signal that is asserted, during use, if the supply voltage to an integrated circuit is to be increased. The switch is configured to electrically couple the first capacitor to the node in response to an assertion of the control signal. When electrically coupled to the node, the first capacitor supplies charge to the bypass capacitors. A system comprising the apparatus, the node, the integrated circuit, and the bypass capacitors is also contemplated in some embodiments.
摘要翻译： 在一个实施例中，提供了一种用于系统的装置，该系统包括耦合到节点的集成电路以接收电源电压并且具有与集成电路并联耦合到节点的旁路电容器。 该装置包括第一电容器，耦合到第一电容器的开关和被配置为对第一电容器充电的电压源。 该开关被耦合以接收在使用期间如果要增加集成电路的电源电压而被断言的控制信号。 开关被配置为响应于控制信号的断言将第一电容器电耦合到节点。 当电耦合到节点时，第一电容器向旁路电容器提供电荷。 在一些实施例中也可以考虑包括该装置，节点，集成电路和旁路电容器的系统。
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