公开(公告)号：US20240095871A1

公开(公告)日：2024-03-21

申请号：US17933409

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Ido Y Soffair ,  Uri Nix ,  Yung-Chin Chen ,  Jim C Chou ,  Jian Zhou ,  Assaf Menachem ,  Sorin C Cismas

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: A device may include a display for displaying an image frame based on warped image data and image processing circuitry to generate the warped image data by warping input image data to account for one or more distortions associated with displaying the image. The image processing circuitry may include a two-stage cache architecture having an first cache and an second cache and warp the input image data by generating mapping data indicative of a warp between the input image space and the output image space and fetching the input image data to populate the first cache. Warping may also include populating the second cache with a grouping of pixel values from the first cache that are selected according to a sliding window that traverses the first cache based on the mapping data and interpolating between pixel values of the grouping to generate pixel values of the warped image data.

公开(公告)号：US11688365B2

公开(公告)日：2023-06-27

申请号：US17466865

申请日：2021-09-03

Applicant: Apple Inc.

Inventor： Assaf Menachem

IPC: G09G5/12 ,  G09G5/14 ,  G09G5/377 ,  G06T1/20

CPC classification number: G09G5/14 ,  G06T1/20 ,  G09G5/12 ,  G09G5/377 ,  G09G2300/026 ,  G09G2320/08 ,  G09G2340/10 ,  G09G2370/20

Abstract: An electronic device may include a first display pipeline that may output image data via an output path. The electronic device may include first frame merge circuitry coupled to the output path. The electronic device may also include a first multiplexer coupled to the first frame merge circuitry and to the output path. The first multiplexer may transmit the image data from the output path to an electronic display, and, in response to a first control signal associated with the first frame merge circuitry generating a merged output, the first multiplexer transmits the merged output to the electronic display.

公开(公告)号：US20230197022A1

公开(公告)日：2023-06-22

申请号：US18109691

申请日：2023-02-14

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

CPC classification number: G09G3/3426 ,  G09G2320/0646 ,  G09G2360/18 ,  G09G2320/0233 ,  G09G2330/021

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

公开(公告)号：US11594189B2

公开(公告)日：2023-02-28

申请号：US17368522

申请日：2021-07-06

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.