公开(公告)号：US11823728B2

公开(公告)日：2023-11-21

申请号：US17687107

申请日：2022-03-04

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C11/40626 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2211/4061

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US20220084474A1

公开(公告)日：2022-03-17

申请号：US17368522

申请日：2021-07-06

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

公开(公告)号：US11270753B2

公开(公告)日：2022-03-08

申请号：US17182341

申请日：2021-02-23

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C7/04 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4091

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US11842700B2

公开(公告)日：2023-12-12

申请号：US18109691

申请日：2023-02-14

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

CPC classification number: G09G3/3426 ,  G09G2320/0233 ,  G09G2320/0646 ,  G09G2330/021 ,  G09G2360/18

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

公开(公告)号：US20220254410A1

公开(公告)日：2022-08-11

申请号：US17687107

申请日：2022-03-04

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4091

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US10175905B2

公开(公告)日：2019-01-08

申请号：US15263833

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Liang Deng ,  Kai Lun Hsiung ,  Manu Gulati ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Venkata Ramana Malladi ,  Gregory S. Mathews ,  Enming Zheng ,  Fabien S. Faure

IPC: G06F1/32 ,  G06F3/06 ,  G06F1/08 ,  G06F13/16 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

公开(公告)号：US10978136B2

公开(公告)日：2021-04-13

申请号：US16515351

申请日：2019-07-18

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C7/04 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4074

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US20240119991A1

公开(公告)日：2024-04-11

申请号：US18488656

申请日：2023-10-17

Applicant: Apple Inc.

Inventor： Liang Deng ,  Norman J. Rohrer ,  Yizhang Yang ,  Arpit Mittal

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4091

CPC classification number: G11C11/40626 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2211/4061

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

公开(公告)号：US20230197022A1

公开(公告)日：2023-06-22

申请号：US18109691

申请日：2023-02-14

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

CPC classification number: G09G3/3426 ,  G09G2320/0646 ,  G09G2360/18 ,  G09G2320/0233 ,  G09G2330/021

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.

公开(公告)号：US11594189B2

公开(公告)日：2023-02-28

申请号：US17368522

申请日：2021-07-06

Applicant: Apple Inc.

Inventor： Prabhu Rajamani ,  Liang Deng ,  Oren Kerem ,  Meir Harar ,  Ido Yaacov Soffair ,  Assaf Menachem ,  John H. Kelm ,  Rohit K. Gupta

IPC: G09G3/34

Abstract: Throttling circuitry may throttle the backlight reconstruction via backlight reconstruction and compensation circuitry in a display pipeline when power may be limited. This throttling of the display pipeline may limit a number of cycles that may be used for performing backlight reconstruction and compensation.