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公开(公告)号：US20250124645A1
公开(公告)日：2025-04-17
申请号：US18988111
申请日：2024-12-19
Applicant: Apple Inc.
Inventor： Christopher A. Burns
Abstract: Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, traversal circuitry is configured to traverse an acceleration data structure that includes hierarchically-arranged bounding volumes for at least a portion of a graphics scene, including to perform a depth-first search of the acceleration data structure for a ray. The traversal may also include, for a set of child nodes of a first node in the acceleration data structure, selecting a next node for the depth-first search according to an ordering of intersected bounding regions for the set of child nodes. The ordering may begin with a bounding volume that is closer to a mid-point of a ray being tested than one or more front bounding volumes and one or more back bounding volumes.
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公开(公告)号：US20250095274A1
公开(公告)日：2025-03-20
申请号：US18524265
申请日：2023-11-30
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Luca O. Iuliano , David J. Bermingham , Christopher A. Burns
Abstract: Techniques are disclosed relating to graphics processors that support ray tracing. In disclosed embodiments, ray intersect circuitry is configured to access a traversal stack used for traversal of multiple levels of a bounding volume hierarchy (BVH) acceleration data structure (ADS) according to a depth-first search to retrieve: coordinates of a first bounding region for a child node and a local ray parameter value that indicates a point along a ray at which an intersection with a second bounding region for the child node's parent node was detected. The accelerator circuitry may compare the local ray parameter value with an end ray parameter value to determine whether to traverse to the child node as part of traversal of the BVH.
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公开(公告)号：US12008377B2
公开(公告)日：2024-06-11
申请号：US18299452
申请日：2023-04-12
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Liang-Kai Wang , Robert D. Kenney , Terence M. Potter
CPC classification number: G06F9/3887 , G06F9/30098 , G06T1/20 , G06T1/60
Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.
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公开(公告)号：US12002190B2
公开(公告)日：2024-06-04
申请号：US17136542
申请日：2020-12-29
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Casper R. W. van Benthem
CPC classification number: G06T7/0002 , G06T1/20 , G06T15/005 , G06T15/06 , G06T17/10 , G06T2207/20224
Abstract: Techniques are disclosed relating to testing whether a ray intersects a graphics primitive, e.g., for ray tracing. In some embodiments, intersection circuitry performs a reduced-precision conservative intersection test and shader circuitry performs an original-precision intersection test if the intersection circuitry indicates a hit. The intersection circuitry may quantize the ray (and may quantize the primitive or may receive a quantized representation of the primitive) and generates a potential error value based on propagation of quantization error for the primitive and ray. The intersection circuitry then determines an intersection result for the reduced-precision test based on the quantized primitive data and the potential error. In various embodiments, disclosed techniques may improve performance or reduce power consumption by reducing the number of original-precision intersection tests that do not result in hits.
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公开(公告)号：US20240046550A1
公开(公告)日：2024-02-08
申请号：US18490548
申请日：2023-10-19
Applicant: Apple Inc.
Inventor： Christopher A. Burns
CPC classification number: G06T15/06 , G06T15/506 , G06T2215/12
Abstract: Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, test circuitry is configured to perform an intersection test based on traversal of an acceleration data structure that includes hierarchically-arranged bounding volumes for a graphics scene, where the test operates on: reduced-precision representations of rays that are quantized versions of initial representations of the rays and reduced-representatives of primitives that are quantized versions of initial representations of the primitives. The test may generate a first result for a first ray and a first primitive that indicates that a line coincident with the first ray definitively intersects the first primitive. The graphics processor may record an intersection for the first ray with the first primitive, based on the first result, without performing an intersection test for the first ray using the initial representation of the first ray and the first primitive.
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Patent Agency Ranking
公开(公告)号：US11830124B2
公开(公告)日：2023-11-28
申请号：US17456503
申请日：2021-11-24
Applicant: Apple Inc.
Inventor： Christopher A. Burns
CPC classification number: G06T15/06 , G06T15/506 , G06T2215/12
Abstract: Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, test circuitry is configured to perform intersection tests that operate on reduced-precision representations of rays that were generated by quantizing initial representations of the rays and reduced-precision representations of primitives that were generated by quantizing initial representations of the primitives. Some reduced-precision tests (e.g., for any-hit rays) may generate a definitive hit according to the initial representations. In this situation, graphics processing circuitry may record an intersection with the reduced-precision representation of the primitive for the ray based on the first result, without performing an intersection test for the first ray using the initial representation of the ray and the primitive. Disclosed techniques may advantageously reduce power consumption, improve performance, or both.
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27.发明授权公开(公告)号：US11436784B2
公开(公告)日：2022-09-06
申请号：US17103406
申请日：2020-11-24
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Luca Iuliano , Jonathan M. Redshaw
IPC: G06T15/06 , G06T15/00 , G06F9/48 , G06F9/50 , G06T1/20 , G06F16/22 , G06F30/31 , G06T17/10 , G16H40/67 , G06Q10/10 , G06Q50/04
Abstract: Disclosed techniques relate to primitive testing associated with ray intersection processing for ray tracing. In some embodiments, shader circuitry executes a first SIMD group that includes a ray intersect instruction for a set of rays. Ray intersect circuitry traverses, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure (ADS). In response to reaching a node of the ADS that indicates one or more primitives, the apparatus forms a second SIMD group that executes one or more instructions to determine whether a set of rays that have reached the node intersect the one or more primitives. The shader circuitry may execute the first SIMD group to shade one or more primitives that are indicated as intersected based on results of execution of the second SIMD group. Thus, disclosed techniques may use both dedicated ray intersect circuitry and dynamically formed SIMD groups executed by shader processors to detect ray intersection.
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公开(公告)号：US11373360B2
公开(公告)日：2022-06-28
申请号：US17103317
申请日：2020-11-24
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Luca Iuliano , Jonathan M. Redshaw
IPC: G06T15/06 , G06T1/20 , G06T15/00 , G06F9/48 , G06F9/50 , G06F16/22 , G06F30/31 , G06T17/10 , G16H40/67 , G06Q10/10 , G06Q50/04
Abstract: Disclosed techniques relate to grouping rays during traversal of a spatially-organized acceleration data structure (e.g., a bounding volume hierarchy) for ray intersection processing. The grouping may provide temporal locality for accesses to bounding region data. In some embodiments, ray intersect circuitry is configured to group rays based on the node of the data structure that they target next. The ray intersect circuitry may select one or more groups of rays for issuance each clock cycle, e.g., to bounding region test circuitry.
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公开(公告)号：US11367242B2
公开(公告)日：2022-06-21
申请号：US17103433
申请日：2020-11-24
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Luca Iuliano , Jonathan M. Redshaw
Abstract: Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques.
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公开(公告)号：US11126439B2
公开(公告)日：2021-09-21
申请号：US16686060
申请日：2019-11-15
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Liang-Kai Wang , Robert D. Kenney , Terence M. Potter
Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.
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