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公开(公告)号：US12217350B2
公开(公告)日：2025-02-04
申请号：US17817742
申请日：2022-08-05
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Luca Iuliano , Jonathan M. Redshaw
IPC: G06T15/06 , G06F9/38 , G06F9/48 , G06F9/50 , G06F16/22 , G06F30/31 , G06T1/20 , G06T1/60 , G06T15/00 , G06T17/00 , G06Q10/101 , G06Q50/04 , G06T17/10 , G16H40/67
Abstract: Disclosed techniques relate to acceleration data structure for ray intersection testing. In some embodiments, storage circuitry stores node data for a spatially organized acceleration data structure, including to store the following node information for a given node: origin coordinates for the node and, for a given child node of multiple child nodes, child information that includes: quantized bounding region information for a bounding region corresponding to the child node, where the quantized bounding region information encodes bounding region coordinates as offsets relative to the origin coordinates. Traversal circuitry may traverse multiple nodes of the data structure and determine whether a ray intersects a bounding region indicated by given a node of the data structure based on the node information. Disclosed techniques may provide substantial improvements to performance, data size, and power consumption.
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公开(公告)号：US12086919B2
公开(公告)日：2024-09-10
申请号：US18344294
申请日：2023-06-29
Applicant: Apple Inc.
Inventor： Arthur Y Zhang , Ray L. Chang , Timothy R. Oriol , Ling Su , Gurjeet S. Saund , Guy Cote , Jim C. Chou , Hao Pan , Tobias Eble , Avi Bar-Zeev , Sheng Zhang , Justin A. Hensley , Geoffrey Stahl
Abstract: A mixed reality system that includes a device and a base station that communicate via a wireless connection The device may include sensors that collect information about the user's environment and about the user. The information collected by the sensors may be transmitted to the base station via the wireless connection. The base station renders frames or slices based at least in part on the sensor information received from the device, encodes the frames or slices, and transmits the compressed frames or slices to the device for decoding and display. The base station may provide more computing power than conventional stand-alone systems, and the wireless connection does not tether the device to the base station as in conventional tethered systems. The system may implement methods and apparatus to maintain a target frame rate through the wireless link and to minimize latency in frame rendering, transmittal, and display.
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公开(公告)号：US11521343B2
公开(公告)日：2022-12-06
申请号：US17103462
申请日：2020-11-24
Applicant: Apple Inc.
Inventor： Terence M. Potter , Yoong Chert Foo , Ali Rabbani Rankouhi , Justin A. Hensley , Jonathan M. Redshaw
IPC: G06F15/16 , G06T15/06 , G06T15/00 , G06F9/48 , G06F9/50 , G06T1/20 , G06F16/22 , G06F30/31 , G06F9/38 , G06T1/60 , G06T17/10 , G16H40/67 , G06Q10/10 , G06Q50/04
Abstract: Disclosed techniques relate to memory space management for graphics processing. In some embodiments, first and second graphics cores are configured to execute instructions for multiple threadgroups. In some embodiments, the threads groups include a first threadgroup with multiple single-instruction multiple-data (SIMD) groups configured to execute a first shader program and a second threadgroup with multiple SIMD groups configured to execute a second, different shader program. Control circuitry may be configured to provide access to data stored in memory circuitry according to a shader memory space. The shader memory space may be accessible to threadgroups executed by the first graphics shader core, including the first and second threadgroups, but is not accessible to threadgroups executed by the second graphics shader core. Disclosed techniques may reduce latency, increase bandwidth available to the shader, reduce coherency cost, or any combination thereof.
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公开(公告)号：US20220036639A1
公开(公告)日：2022-02-03
申请号：US17103433
申请日：2020-11-24
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Christopher A. Burns , Justin A. Hensley , Luca Iuliano , Jonathan M. Redshaw
Abstract: Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques.
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公开(公告)号：US10223822B2
公开(公告)日：2019-03-05
申请号：US15388915
申请日：2016-12-22
Applicant: Apple Inc.
Inventor： Terence M. Potter , Ralph C. Taylor , Richard W. Schreyer , Aaftab A. Munshi , Justin A. Hensley
Abstract: Techniques are disclosed relating to performing mid-render auxiliary compute tasks for graphics processing. In some embodiments, auxiliary compute tasks are performed during a render pass, using at least a portion of a memory context of the render pass, without accessing a shared memory during the render pass. Relative to flushing render data to shared memory to perform compute tasks, this may reduce memory accesses and/or cache thrashing, which may in turn increase performance and/or reduce power consumption.
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Patent Agency Ranking
公开(公告)号：US20180182153A1
公开(公告)日：2018-06-28
申请号：US15388915
申请日：2016-12-22
Applicant: Apple Inc.
Inventor： Terence M. Potter , Ralph C. Taylor , Richard W. Schreyer , Aaftab A. Munshi , Justin A. Hensley
CPC classification number: G06T15/005 , G06F9/5038 , G06F9/5066 , G06F9/544 , G06T1/20 , G06T15/80 , Y02D10/22 , Y02D10/36
Abstract: Techniques are disclosed relating to performing mid-render auxiliary compute tasks for graphics processing. In some embodiments, auxiliary compute tasks are performed during a render pass, using at least a portion of a memory context of the render pass, without accessing a shared memory during the render pass. Relative to flushing render data to shared memory to perform compute tasks, this may reduce memory accesses and/or cache thrashing, which may in turn increase performance and/or reduce power consumption.
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公开(公告)号：US20240045808A1
公开(公告)日：2024-02-08
申请号：US18490588
申请日：2023-10-19
Applicant: Apple Inc.
Inventor： Justin A. Hensley , Karl D. Mann , Yoong Chert Foo , Terence M. Potter , Frank W. Liljeros , Ralph C. Taylor
IPC: G06F12/1018 , G06F12/084
CPC classification number: G06F12/1018 , G06F12/084 , G06F30/392
Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.
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公开(公告)号：US20230253979A1
公开(公告)日：2023-08-10
申请号：US18302513
申请日：2023-04-18
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Karthik Ramani , Stephan Lachowsky , Justin A. Hensley , Davoud A. Jamshidi
IPC: H03M7/30 , H04N19/182 , H04N19/176
CPC classification number: H03M7/3059 , H04N19/182 , H04N19/176
Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.
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公开(公告)号：US11676327B2
公开(公告)日：2023-06-13
申请号：US17205680
申请日：2021-03-18
Applicant: Apple Inc.
Inventor： Christopher A. Burns , Ali Rabbani Rankouhi , Justin A. Hensley , Richard W. Schreyer
IPC: G06T15/06 , G06F16/901 , G06T15/00
CPC classification number: G06T15/06 , G06F16/9027 , G06T15/005
Abstract: Techniques are disclosed relating to ray intersection in the context of motion blur. In some embodiments, a graphics processor includes time-oblivious ray intersect circuitry configured to receive coordinates for a ray and traverse a bounding volume hierarchy (BVH) data structure based on the coordinates to determine whether the ray intersects with one or more bounding regions of a graphics space. In some embodiments, in response to reaching a temporal branch element of the BVH data structure, the ray intersect circuitry initiates a shader program that determines a sub-tree of the BVH data structure for further traversal by the ray intersection circuitry, where the sub-tree corresponds to a portion of a motion-blur interval in which the ray falls. This may provide accurate ray tracing for motion blur while reducing area and power consumption of intersect circuitry, relative to time-aware implementations.
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公开(公告)号：US11664816B2
公开(公告)日：2023-05-30
申请号：US16855540
申请日：2020-04-22
Applicant: Apple Inc.
Inventor： Tyson J. Bergland , Karthik Ramani , Stephan Lachowsky , Justin A. Hensley , Davoud A. Jamshidi
IPC: H03M7/30 , H04N19/182 , H04N19/176
CPC classification number: H03M7/3059 , H04N19/176 , H04N19/182
Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.
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