Codebook subset restriction for enhanced type II channel state information reporting

    公开(公告)号:US11705945B2

    公开(公告)日:2023-07-18

    申请号:US17965147

    申请日:2022-10-13

    Applicant: Apple Inc.

    CPC classification number: H04B7/0456 H04B7/046 H04B7/0626

    Abstract: A base station may transmit to a device an indication of codebook subset restriction (CBSR), which includes at least a restriction on a frequency basis. The device may receive the indication of CBSR, and may transmit to the base station channel state information (CSI) according to the received indication of CBSR. The indication of CBSR may also include a restriction on a spatial basis and restrict the device from reporting the CSI based on a subset of the frequency basis in addition to the spatial basis per configuration of the base station. The indication of CBSR may include a separately configured maximum allowed amplitude of a weighting coefficient for the spatial basis and the frequency basis, where the weighting coefficient is associated with a column vector of a precoding matrix used by the base station and the device. The number of frequency bases and the frequency compression units may be determined based on a number of different criteria, for example the number of antennas, the number of subbands, etc.

    Inter cluster snoop latency reduction

    公开(公告)号:US11537538B2

    公开(公告)日:2022-12-27

    申请号:US17242051

    申请日:2021-04-27

    Applicant: Apple Inc.

    Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g., coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

    Inter cluster snoop latency reduction

    公开(公告)号:US11016913B1

    公开(公告)日:2021-05-25

    申请号:US16834148

    申请日:2020-03-30

    Applicant: Apple Inc.

    Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g. coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

    SYSTEMS AND METHODS FOR PROVIDING DISTRIBUTED GLOBAL ORDERING

    公开(公告)号:US20200081837A1

    公开(公告)日:2020-03-12

    申请号:US16125494

    申请日:2018-09-07

    Applicant: Apple Inc.

    Abstract: Systems, apparatuses, and methods for implementing a distributed global ordering point are disclosed. A system includes at least a communication fabric, sequencing logic, and a plurality of coherence point pipelines. Each coherence point pipeline receives transactions from the communication fabric and then performs coherence operations and a memory cache lookup for the received transactions. The global ordering point of the system is distributed across the outputs of the separate coherence point pipelines. Device-ordered transactions travelling upstream toward memory are assigned sequence numbers by the sequencing logic. The transactions are speculatively issued from the communication fabric to the coherence point pipelines. Speculatively issuing the transactions to the coherence point pipelines may cause the transactions to pass through the distributed global ordering point out of order. Control logic on the downstream path reorders the transactions based on the assigned sequence numbers.

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