公开(公告)号：US20210303486A1

公开(公告)日：2021-09-30

申请号：US17242051

申请日：2021-04-27

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Christopher D. Shuler ,  Srinivasa Rangan Sridharan ,  Yu Zhang ,  Kaushik Kannan ,  Deniz Balkan

IPC: G06F13/16 ,  G06F13/40

Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g., coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

公开(公告)号：US20240126457A1

公开(公告)日：2024-04-18

申请号：US18535697

申请日：2023-12-11

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F3/06 ,  G06F12/0831

CPC classification number: G06F3/0631 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0835 ,  G06F2212/1021

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：US11893251B2

公开(公告)日：2024-02-06

申请号：US17462812

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F3/06 ,  G06F12/0831

CPC classification number: G06F3/0631 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0835 ,  G06F2212/1021

Abstract: A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.

公开(公告)号：US20230062917A1

公开(公告)日：2023-03-02

申请号：US17462812

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F3/06 ,  G06F12/0831

Abstract: A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.

公开(公告)号：US11704245B2

公开(公告)日：2023-07-18

申请号：US17462777

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：US20230067307A1

公开(公告)日：2023-03-02

申请号：US17462777

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Rohit Natarajan ,  Jurgen M. Schulz ,  Christopher D. Shuler ,  Rohit K. Gupta ,  Thomas T. Zou ,  Srinivasa Rangan Sridharan

IPC: G06F12/0802

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：US11537538B2

公开(公告)日：2022-12-27

申请号：US17242051

申请日：2021-04-27

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Christopher D. Shuler ,  Srinivasa Rangan Sridharan ,  Yu Zhang ,  Kaushik Kannan ,  Deniz Balkan

IPC: G06F11/34 ,  G06F13/16 ,  G06F13/40

Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g., coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

公开(公告)号：US11016913B1

公开(公告)日：2021-05-25

申请号：US16834148

申请日：2020-03-30

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Christopher D. Shuler ,  Srinivasa Rangan Sridharan ,  Yu Zhang ,  Kaushik Kannan ,  Deniz Balkan

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

Abstract: In one embodiment, a cache coherent system includes one or more agents (e.g. coherent agents) that may cache data used by the system. The system may include a point of coherency in a memory controller in the system, and thus the agents may transmit read requests to the memory controller to coherently read data. The point of coherency may determine if the data is cached in another agent, and may transmit a copy back request to the other agent if the other agent has modified the data. The system may include an interconnect between the agents and the memory controller. At a point on the interconnect at which traffic from the agents converges, a copy back response may be converted to a fill for the requesting agent.

公开(公告)号：US10298511B2

公开(公告)日：2019-05-21

申请号：US15246046

申请日：2016-08-24

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Christopher D. Shuler ,  Benjamin K. Dodge ,  Thejasvi M. Vijayaraj ,  Harshavardhan Kaushikkar ,  Yang Yang ,  Rong Z. Hu ,  Srinivasa R. Sridharan ,  Wolfgang H. Klingauf ,  Neeraj Parik

IPC: H04W72/12 ,  H04L12/863 ,  G06F13/16 ,  G06F9/54 ,  H04L12/865

Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.

公开(公告)号：US20180063016A1

公开(公告)日：2018-03-01

申请号：US15246046

申请日：2016-08-24

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Christopher D. Shuler ,  Benjamin K. Dodge ,  Thejasvi M. Vijayaraj ,  Harshavardhan Kaushikkar ,  Yang Yang ,  Rong Z. Hu ,  Srinivasa R. Sridharan ,  Wolfgang H. Klingauf ,  Neeraj Parik

IPC: H04L12/863

CPC classification number: H04L47/6295 ,  G06F9/546 ,  G06F13/1642 ,  H04L47/6275

Abstract: In some embodiments, a system includes a memory system, plurality of computing devices, and plurality of queues. The plurality of computing devices perform actions dependent on data stored at the memory device, where traffic between the plurality of computing devices and the memory device has at least a first priority level and a second priority level. The first priority level is higher than the second priority level. The plurality of queues pass data between the memory device and the plurality of computing devices. A particular queue allocates a first portion of the particular queue to traffic having the first priority level and allocates a second portion of the particular queue to traffic having the first priority level and to traffic having the second priority level.