公开(公告)号：US20210126877A1

公开(公告)日：2021-04-29

申请号：US17051028

申请日：2019-05-02

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Tushar P Ringe ,  Phanindra Kumar Mannava ,  Dimitrios Kaseridis

IPC: H04L12/931 ,  G06F13/36 ,  H04L12/801 ,  H04L12/933 ,  H04L12/947

Abstract: An improved protocol for data transfer between a request node and a home node of a data processing network that includes a number of devices coupled via an interconnect fabric is provided that minimizes the number of response messages transported through the interconnect fabric. When congestion is detected in the interconnect fabric, a home node sends a combined response to a write request from a request node. The response is delayed until a data buffer is available at the home node and home node has completed an associated coherence action. When the request node receives a combined response, the data to be written and the acknowledgment are coalesced in the data message.

公开(公告)号：US10970225B1

公开(公告)日：2021-04-06

申请号：US16591827

申请日：2019-10-03

Applicant: Arm Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Jamshed Jalal

IPC: G06F12/0897 ,  G06F12/0868 ,  G06F12/0871 ,  G06F3/06

Abstract: An apparatus and method are provided for handling cache maintenance operations. The apparatus has a plurality of requester elements for issuing requests and at least one completer element for processing such requests. A cache hierarchy is provided having a plurality of levels of cache to store cached copies of data associated with addresses in memory. A requester element may be arranged to issue a cache maintenance operation request specifying a memory address range in order to cause a block of data associated with the specified memory address range to be pushed through at least one level of the cache hierarchy to a determined visibility point in order to make that block of data visible to one or more other requester elements. The given requester element may be arranged to detect when there is a need to issue a write request prior to the cache maintenance operation request in order to cause a write operation to be performed in respect of data within the specified memory address range, and in that event to generate a combined write and cache maintenance operation request to be issued instead of the write request and a subsequent cache maintenance operation request. A recipient completer element that receives the combined write and cache maintenance operation request may then be arranged to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete. This can significantly reduce latency in the handling of cache maintenance operations, and can provide for reduced bandwidth utilisation.

公开(公告)号：US10324858B2

公开(公告)日：2019-06-18

申请号：US15620017

申请日：2017-06-12

Applicant: ARM LIMITED

Inventor： Bruce James Mathewson ,  Phanindra Kumar Mannava ,  Matthew Lucien Evans ,  Paul Gilbert Meyer ,  Andrew Brookfield Swaine

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/0802 ,  G06F12/14 ,  G06F13/16

Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

公开(公告)号：US10223002B2

公开(公告)日：2019-03-05

申请号：US15427335

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar Mannava ,  Bruce James Mathewson ,  Klas Magnus Bruce ,  Geoffray Matthieu Lacourba

IPC: G06F3/06 ,  G06F12/06 ,  G06F9/52

Abstract: A compare and swap transaction can be issued by a master device to request a processing unit to select whether to write a swap data value to a storage location corresponding to a target address in dependence on whether a compare data value matches a target data value read from the storage location. The compare and swap data values are transported within a data field of the compare and swap transaction. The compare data value is packed into a first region of the data field in dependence of an offset portion of the target address and having a position within the data field corresponding to the position of the target data value within the storage location. This reduces latency and circuitry required at the processing unit for handling the compare and swap transaction.

公开(公告)号：US10042766B1

公开(公告)日：2018-08-07

申请号：US15422691

申请日：2017-02-02

Applicant: ARM Limited

Inventor： Tushar P. Ringe ,  Jamshed Jalal ,  Klas Magnus Bruce ,  Phanindra Kumar Mannava

IPC: G06F13/00 ,  G06F12/0831 ,  G06F15/78 ,  G06F12/0868 ,  G06F13/42 ,  G06F13/16 ,  G06F12/06 ,  G06F13/38

Abstract: A home node of a data processing apparatus that includes a number of devices coupled via an interconnect system is configured to provide efficient transfer of data to a first device from a second device. The home node is configured dependent upon data bus widths of the first and second devices and the data bus width of the interconnect system. Data is transferred as a cache line serialized into a number of data beats. The home node may be configured to minimize the number of data transfers on the third data bus or to minimize latency in the transfer of the critical beat of the cache line.