公开(公告)号：US06511876B2

公开(公告)日：2003-01-28

申请号：US09888777

申请日：2001-06-25

申请人： Douglas A. Buchanan ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Deborah Ann Neumayer

发明人： Douglas A. Buchanan ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Deborah Ann Neumayer

IPC分类号： H01C218242

CPC分类号： H01L21/28185 ,  H01L21/02178 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31616 ,  H01L21/3162 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming a high-k dielectric material which exhibits a substantially lower amount of trap charge within a gate stack region is provided. The method maintains high-temperatures (250° C. or above) such that the substrate wafer is not cooled during the various processing steps. Such a method leads to the formation of a high-k dielectric material which does not exhibit a hysteric behavior in a capacitance-voltage curve as well as an increased mobility on FETs using conventional CMOS processing.

摘要翻译： 提供了一种形成在栅极堆叠区域内呈现基本较低量的陷阱电荷的高k电介质材料的方法。 该方法保持高温（250℃或以上），使得在各种处理步骤期间基板晶片不被冷却。 这种方法导致形成高k电介质材料，其在电容 - 电压曲线中不表现出歇斯底里行为，并且使用常规CMOS处理在FET上增加迁移率。